Kyösti Mälkki said:
AFAICS, that platform codebase even suffers from cache coherency issues while executing from cache-as-ram; there has been indications that increased spinlock usage in romstage causes boot failures and/or reset loops.
Where do you see this? Has it been reported?
Implementation of HyperTransport requires maintaining some pretty strange
(or poor-quality) code for both static devicetree and PCI subsystem.
Which code? How can it be improved?
Sincerely, -Matthew Bradley
On Wed, Sep 18, 2019 at 6:25 PM Kyösti Mälkki kyosti.malkki@gmail.com wrote:
On Thu, Sep 19, 2019 at 1:05 AM Martin Roth martinroth@google.com wrote:
My proposal is to drop platforms that aren't being tested, aren't being maintained, or are causing serious problems with general coreboot development.
For example
- ASUS KGPE-d16 is still being used and tested, so I wouldn't suggest
dropping that code, even though it apparently doesn't support S3, so it was suggested that we drop it. S3 isn't used heavily on servers, so personally I don't think it matters.
Nothing to do with S3 for asus/kgpe-d16 deprecation.
Platform code (non-AGESA) fam10-15 does not meet 3 of the 3 announced requirements for next release. Should someone want to maintain kgpe-d16 on master branch, the decisions on those release requirements will need to be officially withdrawn. AFAICS, that platform codebase even suffers from cache coherency issues while executing from cache-as-ram; there has been indications that increased spinlock usage in romstage causes boot failures and/or reset loops.
Implementation of HyperTransport requires maintaining some pretty strange (or poor-quality) code for both static devicetree and PCI subsystem.
Regards, Kyösti Mälkki _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org