If you get a chance, there's a note in the 440bx spec update that is of some minor interest:
13. Abort Disable Test Mode Configuration Bits Intel Reserved Register bits at offset F4h, bits 29 and 30 should be set to 1 for normal operation.
It could be (most likely) is nothing, as my current lspci shows it not being set, but it might just help. Damn reserved/undocumented registers.