Author: rminnich Date: 2008-08-15 23:40:20 +0200 (Fri, 15 Aug 2008) New Revision: 772
Added: coreboot-v3/southbridge/amd/amd8151/ coreboot-v3/southbridge/amd/amd8151/Makefile coreboot-v3/southbridge/amd/amd8151/agpbridge.dts coreboot-v3/southbridge/amd/amd8151/agpdev.dts coreboot-v3/southbridge/amd/amd8151/amd8151_agp3.c Modified: coreboot-v3/arch/x86/Kconfig coreboot-v3/southbridge/amd/amd8111/amd8111.c coreboot-v3/southbridge/amd/amd8132/amd8132_bridge.c Log: Some corrections to the 8132.
Add the 8152.
Add a config variable ACPI_TABLE
Signed-off-by: Ronald G. Minnich rminnich@gmail.com Acked-by: Ronald G. Minnich rminnich@gmail.com
Modified: coreboot-v3/arch/x86/Kconfig =================================================================== --- coreboot-v3/arch/x86/Kconfig 2008-08-15 21:18:26 UTC (rev 771) +++ coreboot-v3/arch/x86/Kconfig 2008-08-15 21:40:20 UTC (rev 772) @@ -129,6 +129,13 @@ a PIRQ table, which is the old way to set up interrupt routing. It is usually set in mainboard/*/Kconfig.
+config ACPI_TABLE + boolean + help + This option is used to determine whether the mainboard has + an ACPI table. + It is usually set in mainboard/*/Kconfig. + config SMP boolean default 0
Modified: coreboot-v3/southbridge/amd/amd8111/amd8111.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/amd8111.c 2008-08-15 21:18:26 UTC (rev 771) +++ coreboot-v3/southbridge/amd/amd8111/amd8111.c 2008-08-15 21:40:20 UTC (rev 772) @@ -92,7 +92,7 @@ } }
-struct device_operations mcp55_ide = { +struct device_operations amd8111 = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_AMD_8111_PCI}}},
Modified: coreboot-v3/southbridge/amd/amd8132/amd8132_bridge.c =================================================================== --- coreboot-v3/southbridge/amd/amd8132/amd8132_bridge.c 2008-08-15 21:18:26 UTC (rev 771) +++ coreboot-v3/southbridge/amd/amd8132/amd8132_bridge.c 2008-08-15 21:40:20 UTC (rev 772) @@ -345,19 +345,6 @@ } #endif /* BRIDGE_40_BIT_SUPPORT */
-static struct device_operations pcix_ops = { -#if BRIDGE_40_BIT_SUPPORT - .read_resources = bridge_read_resources, - .set_resources = bridge_set_resources, -#else - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, -#endif - .enable_resources = , - .init = , - .scan_bus = , -}; - struct device_operations amd8132_pcix = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD,
Added: coreboot-v3/southbridge/amd/amd8151/Makefile =================================================================== --- coreboot-v3/southbridge/amd/amd8151/Makefile (rev 0) +++ coreboot-v3/southbridge/amd/amd8151/Makefile 2008-08-15 21:40:20 UTC (rev 772) @@ -0,0 +1,27 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 coresystems GmbH +## (Written by Stefan Reinauer stepan@coresystems.de for coresystems GmbH) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8151),y) + +STAGE2_CHIPSET_SRC += $(src)/southbridge/amd/amd8151/amd8151_agp3.c + + +endif
Added: coreboot-v3/southbridge/amd/amd8151/agpbridge.dts =================================================================== --- coreboot-v3/southbridge/amd/amd8151/agpbridge.dts (rev 0) +++ coreboot-v3/southbridge/amd/amd8151/agpbridge.dts 2008-08-15 21:40:20 UTC (rev 772) @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Ronald G. Minnich rminnich@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +{ + device_operations = "amd8151_agp3bridge"; +};
Added: coreboot-v3/southbridge/amd/amd8151/agpdev.dts =================================================================== --- coreboot-v3/southbridge/amd/amd8151/agpdev.dts (rev 0) +++ coreboot-v3/southbridge/amd/amd8151/agpdev.dts 2008-08-15 21:40:20 UTC (rev 772) @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Ronald G. Minnich rminnich@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +{ + device_operations = "amd8151_agp3dev"; +};
Added: coreboot-v3/southbridge/amd/amd8151/amd8151_agp3.c =================================================================== --- coreboot-v3/southbridge/amd/amd8151/amd8151_agp3.c (rev 0) +++ coreboot-v3/southbridge/amd/amd8151/amd8151_agp3.c 2008-08-15 21:40:20 UTC (rev 772) @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Yinghai Lu, Tyan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/pci.h> +#include <msr.h> +#include <legacy.h> +#include <device/pci_ids.h> +#include <statictree.h> +#include <config.h> +#include "mcp55.h" + +static void agp3bridge_init(struct device * dev) +{ + u8 byte; + + /* Enable BM, MEM and IO */ + /* this config32 is arguably wrong but I won't change until we can test. */ + byte = pci_read_config32(dev, 0x04); + byte |= 0x07; + pci_write_config8(dev, 0x04, byte); + + return; +} + +struct device_operations amd8151_agp3bridge = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_8151_AGP}}}, + .constructor = default_device_constructor, + .phase3_scan = pci_scan_bridge + .phase4_read_resources = pci_bus_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = pci_bus_enable_resources, + .phase6_init = agp3bridge_init, +}; + +static void agp3dev_enable(struct device * dev) +{ + u32 value; + + /* AGP enable */ + value = pci_read_config32(dev, 0xa8); + value |= (3<<8)|2; //AGP 8x + pci_write_config32(dev, 0xa8, value); + + /* enable BM and MEM */ + value = pci_read_config32(dev, 0x4); + value |= 6; + pci_write_config32(dev, 0x4, value); +#if 0 + /* FIXME: should we add agp aperture base and size here ? + * or it is done by AGP drivers */ +#endif +} + +static struct pci_operations pci_ops_pci_dev = { + .set_subsystem = pci_dev_set_subsystem, +}; + +struct device_operations amd8151_agp3dev = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_8151_SYSCTRL}}}, + .constructor = default_device_constructor, + .phase4_enable_disable = agp3dev_enable, + .phase4_read_resources = pci_dev_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = pci_dev_enable_resources, + .phase6_init = NULL, + .ops_pci = &pci_dev_ops_pci, +};