Re: [coreboot] patch: two bugs in the cs5536 ide code

[Peter Stuge]

On Wed, May 07, 2008 at 02:42:24AM +0200, Carl-Daniel Hailfinger wrote:
> +++ LinuxBIOSv3-hierarchical_dts/mainboard/amd/norwich/dts	(working copy)
> @@ -34,7 +34,6 @@
>    	};
>    	pci@15,0 {
>    		/config/("southbridge/amd/cs5536/dts");
> 	enable_ide = "1";
> /* Interrupt enables for LPC bus.
>  *  Each bit is an IRQ 0-15. */
> lpc_serirq_enable = "0x00001002";
>
> @@ -50,5 +49,9 @@
>    		com1_address = "0x3f8";
>    		com1_irq = "4";
>    	};
> pci@15,2 {
> 	/config/("southbridge/amd/cs5536/ide");
> 	enable_ide = "1";
> };
> };
>
> };

This makes more sense, but..

What was the reason for introducing multiple dts files for a single
chip again?

Only the C struct name limitations?

*scratches forehead* I kind of want the single dts per chip back..

//Peter