Re: [coreboot] ASRock e350m1 problems

[Scott Duplichan]

Tadas Slotkus wrote:

]> Just to completely rule out the bad SPD idea, can you please dump the
]> SPD content when you boot with the production BIOS? i2cdump output
]> (ASCII) or raw output from sysfs would be great. Then we can plug it
]> into bc and confirm that the checksum is correct. This would also be a
]> good way to confirm that the SPD addresses are correct in Coreboot,
]> and rule out the possibility that ASRock changed SPD addressing
]> between board revisions...
]
]Attaching /sys/bus/i2c/drivers/eeprom/0-0050/eeprom as hex file
]+ i2cdump output

Hello Tadas,

Thanks for the data. I think DIMM SPD check bytes are OK. This SPD has
bit zero of byte zero set, which means the crc covers the first 117 bytes
instead of the first 126 bytes. The old simnow I have seems to not handle
this case.

The original log file you sent also suggests no SPD check byte problem.
A check byte fail creates a error record like this:

EventLog:  EventClass = 5, EventInfo = 4011200.
  Param1 = 0, Param2 = 0.
  Param3 = 0, Param4 = 0.
In addition, your experiment with disabling the check byte confirmation 
did not let it boot.

It seems like it might not be able to read SPD at all. It is possible
your DIMM has SMBus signaling difficulty when run at 400 KHz. You could
try running the SMBus at the default frequency (93750 KHz) by removing
the last statement in function setupFch in file dimmSpd.c:

static void setupFch (int ioBase)
   {
   writePmReg (0x2D, ioBase >> 8);
   writePmReg (0x2C, ioBase | 1);
   writePmReg (0x29, 0x80);
   writePmReg (0x28, 0x61);
   __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to
400 KHz
   }

If that doesn't solve the problem, I would add some code to log each SPD
byte as it is read.

Thanks,
Scott