Author: rminnich Date: 2007-05-08 18:04:36 +0200 (Tue, 08 May 2007) New Revision: 2640
Modified: trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/irq_tables.c Log: New irq table, and a correct setting for the 5c register in the southbridge so that interrupts are routed correctly. With this patch, ethernet works quite well. Signed-off-by: Ronald G. Minnich rminnich@gmail.com
Acked-by: Stefan Reinauer stepan@coresystems.de
Modified: trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/irq_tables.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/irq_tables.c 2007-05-07 22:26:46 UTC (rev 2639) +++ trunk/LinuxBIOSv2/src/mainboard/digitallogic/msm800sev/irq_tables.c 2007-05-08 16:04:36 UTC (rev 2640) @@ -1,65 +1,3 @@ -#if 0 -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up - * - * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ - -#include <arch/pirq_routing.h> - -#define ID_SLOT_PCI_NET 1 // ThinCan ethernet -#define ID_SLOT_PCI_RSVD1 2 // reserved entry 1 -#define ID_SLOT_PCI_RSVD3 3 // reserved entry 2 -#define ID_SLOT_PCI_RSVD2 4 // reserved entry 3 -#define ID_EMBED_PCI 0xff // onboard PCI device - -// CS5535 PCI INT[A-D] Interrupt Routing lines. -#define NO_CONNECT 0 // not used -#define CS_PCI_INTA 1 // PCI INTA -#define CS_PCI_INTB 2 // PCI INTB -#define CS_PCI_INTC 3 // PCI INTC -#define CS_PCI_INTD 4 // PCI INTD - -// IRQ bitmap reference line FEDCBA9876543210 -// 0000110000100000b -#define PCI_IRQ 0xc20 // PCI allowed IRQs here - -const struct irq_routing_table intel_irq_routing_table = -{ - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*6, /* there can be total 2 devices on the bus */ - 0x00, /* Where the interrupt router lies (bus) */ - (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */ - 0x0800, /* IRQs devoted exclusively to PCI usage */ - 0x1022, /* Vendor */ - 0x208f, /* Device */ - 0x00000000, /* Crap (miniport) */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0xdf, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ - { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - // Geode GX3 Host Bridge and VGA Graphics - {0, 0x01<<3, {{CS_PCI_INTA, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}}, ID_EMBED_PCI, 0x0}, - // Realtek RTL8100/8139 Network Controller - {0, 0x0d<<3, {{CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}}, ID_SLOT_PCI_NET, 0x0}, - // Reserved for future extensions - {0, 0x0c<<3, {{CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}}, ID_SLOT_PCI_RSVD1, 0x0}, - // Geode CS5535/CS5536 IO Companion: USB controllers, IDE, Audio. - {0, 0x0f<<3, {{CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}}, ID_EMBED_PCI, 0x0}, - // Reserved for future extensions - {0, 0x0e<<3, {{CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}}, ID_SLOT_PCI_RSVD2, 0x0}, - // Reserved for future extensions - {0, 0x0b<<3, {{CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}}, ID_SLOT_PCI_RSVD3, 0x0} - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr); -} -#endif /* * This file is part of the LinuxBIOS project. * @@ -104,31 +42,34 @@ #define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*IRQ_SLOT_COUNT, /* there can be total 6 devices on the bus */ - 0x00, /* Where the interrupt router lies (bus) */ - (0x0F<<3)|0x0, /* Where the interrupt router lies (dev) */ - 0x00, /* IRQs devoted exclusively to PCI usage */ - 0x100B, /* Vendor */ - 0x002B, /* Device */ - 0, /* Crap (miniport) */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ - { - /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */ - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x01<<3)|0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ - {0x00,(0x0F<<3)|0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ - {0x00,(0x0C<<3)|0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x1, 0x0}, /* slot1 */ - {0x00,(0x0D<<3)|0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x2, 0x0}, /* slot2 */ - {0x00,(0x0A<<3)|0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x3, 0x0}, /* slot3 */ - {0x00,(0x0B<<3)|0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0}, /* slot4 */ - } + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*9, /* There can be total 9 devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x0f<<3)|0x0, /* Where the interrupt router lies (dev) */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x100b, /* Vendor */ + 0x2b, /* Device */ + 0, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xe, /* u8 checksum. This has to be set to some + value that would give 0 after the sum of all + bytes for this structure (including checksum) */ + { + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00,(0x01<<3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, + {0x00,(0x0f<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x00800}}, 0x0, 0x0}, + {0x00,(0x13<<3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, + {0x00,(0x12<<3)|0x0, {{0x03, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, + {0x00,(0x11<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, + {0x00,(0x0a<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x00800}}, 0x1, 0x0}, + {0x00,(0x0b<<3)|0x0, {{0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x0800}, {0x01, 0x00400}}, 0x2, 0x0}, + {0x00,(0x0c<<3)|0x0, {{0x03, 0x0400}, {0x04, 0x0800}, {0x01, 0x0400}, {0x02, 0x00800}}, 0x3, 0x0}, + {0x00,(0x0d<<3)|0x0, {{0x04, 0x0800}, {0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x00400}}, 0x4, 0x0}, + } };
- unsigned long write_pirq_routing_table(unsigned long addr){ int i, j, k, num_entries; unsigned int pirq[4]; @@ -140,7 +81,7 @@
/* Set up chipset IRQ steering */ pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C; - chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA); + chipset_irq_map = (11 << 12 | 10 << 8 | 11 << 4 | 10); printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr, chipset_irq_map); outl(pciAddr & ~3, 0xCF8); outl(chipset_irq_map, 0xCFC); @@ -162,4 +103,5 @@
/* put the PIR table in memory and checksum */ return pirtable_end; -} \ No newline at end of file +} +