Author: myles Date: 2009-07-07 19:54:26 +0200 (Tue, 07 Jul 2009) New Revision: 4406
Added: trunk/coreboot-v2/src/northbridge/via/vx800/pci_rawops.h trunk/coreboot-v2/targets/via/epia-m700/Config-abuild.lb Modified: trunk/coreboot-v2/src/mainboard/via/epia-m700/cache_as_ram_auto.c trunk/coreboot-v2/src/northbridge/via/vx800/dram_init.c trunk/coreboot-v2/src/northbridge/via/vx800/examples/chipset_init.c trunk/coreboot-v2/src/northbridge/via/vx800/uma_ram_setting.c Log: Add pci_rawops.h from the mailing list and fix the via/epia-m700 build.
Signed-off-by: Myles Watson mylesgw@gmail.com Acked-by: Myles Watson mylesgw@gmail.com
Modified: trunk/coreboot-v2/src/mainboard/via/epia-m700/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/cache_as_ram_auto.c 2009-07-07 16:15:43 UTC (rev 4405) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/cache_as_ram_auto.c 2009-07-07 17:54:26 UTC (rev 4406) @@ -43,7 +43,7 @@ #include "pc80/udelay_io.c" #include "lib/delay.c" #if CONFIG_USE_INIT == 0 -#include "lib/memcpy.c" +#include <string.h> #endif #include "cpu/x86/lapic/boot_cpu.c"
@@ -208,21 +208,6 @@ #endif }
-/* !!FIXME!! - * This is a bogus definition to get it to compile. - */ - -struct VIA_PCI_REG_INIT_TABLE { - u8 and_val; - u8 or_val; - u8 bus; - u8 dev; - u8 func; - u8 reg; - u8 v1; - u8 v2; -}; - /* * Added this table 2008-11-28. * This table contains the value needed to be set before begin to init DRAM.
Modified: trunk/coreboot-v2/src/northbridge/via/vx800/dram_init.c =================================================================== --- trunk/coreboot-v2/src/northbridge/via/vx800/dram_init.c 2009-07-07 16:15:43 UTC (rev 4405) +++ trunk/coreboot-v2/src/northbridge/via/vx800/dram_init.c 2009-07-07 17:54:26 UTC (rev 4406) @@ -17,7 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include "lib/memset.c" CB_STATUS DDR2_DRAM_INIT() { CB_STATUS Status;
Modified: trunk/coreboot-v2/src/northbridge/via/vx800/examples/chipset_init.c =================================================================== --- trunk/coreboot-v2/src/northbridge/via/vx800/examples/chipset_init.c 2009-07-07 16:15:43 UTC (rev 4405) +++ trunk/coreboot-v2/src/northbridge/via/vx800/examples/chipset_init.c 2009-07-07 17:54:26 UTC (rev 4406) @@ -93,12 +93,12 @@ 0x00, 0xFF, NB_PXPTRF_REG(0x84), 0x00, 0x28, 0x00, 0xFF, NB_PXPTRF_REG(0x85), 0x00, 0xC0, 0x00, 0xFF, NB_MSGC_REG(0xA3), 0x00, 0x01, // RWAKEEN -// 0x00, 0xFF, NB_PXPTRF_REG(0x64), 0x40, 0x00, //RTDNP2B32EN +// 0x00, 0xFF, NB_PXPTRF_REG(0x64), 0x40, 0x00, //RTDNP2B32EN 0x00, 0xFF, NB_PXPTRF_REG(0xF3), 0xFC, 0x20, 0x00, 0xFF, NB_PXPTRF_REG(0x85), 0x00, 0x00, //RP2P1ABORT
-// fine-tune +// fine-tune // If no settings, C7 will hang or reboot in XP, but CN will not. 0x00, 0xFF, NB_HOST_REG(0x51), 0x84, 0x00, 0x00, 0xFF, NB_HOST_REG(0x52), 0x0F, 0x03, @@ -108,8 +108,8 @@ 0x00, 0xFF, NB_HOST_REG(0x5C), 0x10, 0x10, 0x00, 0xFF, NB_HOST_REG(0x5F), 0x0E, 0x08, 0x00, 0xFF, NB_HOST_REG(0x92), 0xFF, 0x04, // ACPI Base addr - 0x00, 0xFF, NB_HOST_REG(0x97), 0x01, 0x01, // APIC MSI - 0x00, 0xFF, NB_HOST_REG(0x99), 0x02, 0x00, // APIC MSI + 0x00, 0xFF, NB_HOST_REG(0x97), 0x01, 0x01, // APIC MSI + 0x00, 0xFF, NB_HOST_REG(0x99), 0x02, 0x00, // APIC MSI //GTL 0x00, 0xFF, NB_HOST_REG(0x73), 0xFF, 0x66, 0x00, 0xFF, NB_HOST_REG(0xB2), 0xFF, 0x33, @@ -163,9 +163,9 @@ 0x00, 0xFF, SB_LPC_REG(0x67), 0x03, 0x01,
- 0x00, 0xFF, SB_LPC_REG(0x50), 0x7E, 0x00, // Setting PCI device enable - 0x00, 0xFF, SB_LPC_REG(0x51), 0xD0, 0x00, // Setting PCI device enable - 0x00, 0xFF, SB_VLINK_REG(0xD1), 0x04, 0x00, // Setting HDAC enable + 0x00, 0xFF, SB_LPC_REG(0x50), 0x7E, 0x00, // Setting PCI device enable + 0x00, 0xFF, SB_LPC_REG(0x51), 0xD0, 0x00, // Setting PCI device enable + 0x00, 0xFF, SB_VLINK_REG(0xD1), 0x04, 0x00, // Setting HDAC enable {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table };
@@ -249,8 +249,8 @@ { device_t_raw rawdevice = 0; u8 sbchiprev; - rawdevice = PCI_DEV(0, 0x11, 0); - // Set the PMIO base io address + rawdevice = PCI_RAWDEV(0, 0x11, 0); + // Set the PMIO base io address pci_rawmodify_config16(rawdevice, 0x88, VX800_ACPI_IO_BASE, 0xff80); // Enable PMIO @@ -277,13 +277,13 @@ device_t_raw rawdevice = 0; u8 nbchiprev; u32 subid = 0; - rawdevice = PCI_DEV(0, 0, 4); + rawdevice = PCI_RAWDEV(0, 0, 4); nbchiprev = pci_rawread_config8(rawdevice, 0xf6); printk_debug("NB chip revision =%x\n", nbchiprev);
via_pci_inittable(nbchiprev, mNbStage2InitTable);
- rawdevice = PCI_DEV(0, 0, 0); + rawdevice = PCI_RAWDEV(0, 0, 0);
subid = PCI_DEVICE_ID_VIA_VX855_D0F0 << 16 + PCI_VENDOR_ID_VIA; pci_rawwrite_config32(rawdevice, 0x2C, subid); @@ -295,15 +295,15 @@
void IDECSupportOption(u8 sbchiprev) { - pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x50, 0, 0x08); + pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0, 0x08);
- pci_rawmodify_config8(PCI_DEV(0, 0xf, 0), 0x45, 0x00, 0x80); - pci_rawmodify_config8(PCI_DEV(0, 0xf, 0), 0x0A, 0x01, 0xFF); - pci_rawmodify_config8(PCI_DEV(0, 0xf, 0), 0x45, 0x80, 0x00); - pci_rawmodify_config8(PCI_DEV(0, 0xf, 0), 0x40, 0x02, 0x00); + pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x45, 0x00, 0x80); + pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x0A, 0x01, 0xFF); + pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x45, 0x80, 0x00); + pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x40, 0x02, 0x00);
- pci_rawmodify_config8(PCI_DEV(0, 0xf, 0), 0x09, 0x00, 0x05); //COMPATIBLE MODE -// pci_rawmodify_config8(PCI_DEV(0, 0xf, 0), 0x09, 0x05, 0x05);//native MODE + pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x09, 0x00, 0x05); //COMPATIBLE MODE +// pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x09, 0x05, 0x05);//native MODE
via_pci_inittable(sbchiprev, IDEC_INIT); } @@ -350,23 +350,23 @@ Mask = 0x0; Value = 0x1 << BitShift; } - pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x50, Value, Mask); + pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, Value, Mask);
if (bEnable) { D16 = 0; - pci_rawwrite_config16(PCI_DEV(0, 0x10, BaseAddress), + pci_rawwrite_config16(PCI_RAWDEV(0, 0x10, BaseAddress), 0x20, D16);
// Config some Control Register Mask = 0x00; Value = 0x12;
- pci_rawmodify_config8(PCI_DEV(0, 0x10, BaseAddress), + pci_rawmodify_config8(PCI_RAWDEV(0, 0x10, BaseAddress), 0x41, Value, Mask); Mask = 0x00; Value = 0xEB; - pci_rawmodify_config8(PCI_DEV(0, 0x10, BaseAddress), + pci_rawmodify_config8(PCI_RAWDEV(0, 0x10, BaseAddress), 0x4B, Value, Mask); } return; @@ -407,13 +407,13 @@ Mask = 0x0; Value = 0x1 << 1; } - pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x50, Value, Mask); + pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, Value, Mask);
if (bEnable) { // Get Chipset Revision EHCIRevision = - pci_rawread_config8(PCI_DEV(0, 0x10, 4), 0xF6); + pci_rawread_config8(PCI_RAWDEV(0, 0x10, 4), 0xF6); printk_debug("EHCI Revision =%x\n", EHCIRevision); via_pci_inittable(EHCIRevision, mEHCIInitTable); } @@ -475,9 +475,9 @@ { u8 HpetEnable = HPET_ENABLE_BIT; u16 HpetBase = HPET_BASE_ADDRESS; - pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), R_SB_HPET_CONTROL, + pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), R_SB_HPET_CONTROL, HpetEnable); - pci_rawwrite_config16(PCI_DEV(0, 0x11, 0), + pci_rawwrite_config16(PCI_RAWDEV(0, 0x11, 0), R_SB_HPET_ADDRESS + 1, HpetBase); }
@@ -499,7 +499,7 @@ 0x00, 0xFF, SB_LPC_REG(0xE2), 0x00, 0xEA,
0x00, 0xFF, SB_LPC_REG(0xE7), 0x00, 0x80, - {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table + {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table };
void InitPMU(u8 sbchiprev) @@ -512,7 +512,7 @@ // Set SCI IRQ and its level trigger Mask = 0x0F; Value = 0x09; - pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x82, Value, Mask); + pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x82, Value, Mask);
Mask = 0x02; Value = 0x02; @@ -533,7 +533,7 @@ // Now it is C2 & C4 Up Down Mode Mask = 0xFF; Value = 0x30; - pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), R_SB_CX_STATE_BREAK_EVENT_ENABLE_1, Value, Mask); //SB_LPC_REG + pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), R_SB_CX_STATE_BREAK_EVENT_ENABLE_1, Value, Mask); //SB_LPC_REG
Mask = 0xFF; Value = 0x1F; @@ -542,15 +542,15 @@
Mask = 0x00; Value = 0x80; - pci_rawmodify_config8(PCI_DEV(0, 0x11, 7), R_SB_PCI_ARBITRATION_2, Value, Mask); //SB_VLINK_REG + pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 7), R_SB_PCI_ARBITRATION_2, Value, Mask); //SB_VLINK_REG
Mask = 0xFF; Value = 0x00; - pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), R_SB_MULTI_FUNCTION_SELECT_1, Value, Mask); //SB_VLINK_REG + pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), R_SB_MULTI_FUNCTION_SELECT_1, Value, Mask); //SB_VLINK_REG
Mask = 0xFF; Value = 0x1F; - pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), R_SB_AUTO_SWITCH_P_STATE, Value, Mask); //SB_VLINK_REG + pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), R_SB_AUTO_SWITCH_P_STATE, Value, Mask); //SB_VLINK_REG }
void InitSBPM(u8 sbchiprev) @@ -565,7 +565,7 @@ device_t_raw rawdevice = 0; u8 sbchiprev;
- rawdevice = PCI_DEV(0, 11, 0); + rawdevice = PCI_RAWDEV(0, 11, 0); sbchiprev = pci_rawread_config8(rawdevice, 0xf6); printk_debug("SB chip revision =%x\n", sbchiprev);
@@ -585,7 +585,7 @@
HpetInit();
- //pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x50, 0x76, 0);//SB_VLINK_REG + //pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x76, 0);//SB_VLINK_REG
}
@@ -593,8 +593,8 @@ void init_VIA_chipset(void) { printk_debug("In: init_VIA_chipset\n"); - //1.nbstage1 is done in raminit. - //2.sbstage1 + //1.nbstage1 is done in raminit. + //2.sbstage1 AcpiInit(); //3.nbstage2 Stage2NbInit(); @@ -603,18 +603,18 @@ Stage2SbInit();
//5.open hdac - pci_rawmodify_config32(PCI_DEV(0, 0x11, 7), 0xd1, 0, 0x04); + pci_rawmodify_config32(PCI_RAWDEV(0, 0x11, 7), 0xd1, 0, 0x04); printk_debug("End: init_VIA_chipset\n"); }
/** * @brief Main function of the DRAM part of coreboot. * - * Coreboot is divided into Pre-DRAM part and DRAM part. + * Coreboot is divided into Pre-DRAM part and DRAM part. * - * + * * Device Enumeration: - * In the dev_enumerate() phase, + * In the dev_enumerate() phase, */
void hardwaremain(int boot_complete) @@ -634,27 +634,27 @@
#if 0
- pci_rawwrite_config8(PCI_DEV(0, 0, 4), 0xa3, 0x80); - pci_rawwrite_config8(PCI_DEV(0, 17, 7), 0x60, 0x20); - pci_rawwrite_config8(PCI_DEV(0, 17, 7), 0xE5, - pci_rawread_config8(PCI_DEV(0, 3, 0), + pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), 0xa3, 0x80); + pci_rawwrite_config8(PCI_RAWDEV(0, 17, 7), 0x60, 0x20); + pci_rawwrite_config8(PCI_RAWDEV(0, 17, 7), 0xE5, + pci_rawread_config8(PCI_RAWDEV(0, 3, 0), 0x88)); #endif
- pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x51, 0x40, 0x40); //close CE-ATA (Consumer Electronics-ATA) and NFC + pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x51, 0x40, 0x40); //close CE-ATA (Consumer Electronics-ATA) and NFC
- //pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x50, 0x0, 0x40);//open USB Device Mode Enable - pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x50, 0x40, 0x40); //close USB Device Mode + //pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x0, 0x40);//open USB Device Mode Enable + pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x40, 0x40); //close USB Device Mode
- //pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x50, 0x04, 0x04);//close USB 1.1 UHCI Port 4-5 - //pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x50, 0x02, 0x02);//close USB 2.0 ehci + //pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x04, 0x04);//close USB 1.1 UHCI Port 4-5 + //pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x02, 0x02);//close USB 2.0 ehci
- //pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x50, 0x00, 0x76);//open all usb and usb mode - //pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x50, 0x76, 0x76);//close all usb + //pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x00, 0x76);//open all usb and usb mode + //pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x76, 0x76);//close all usb
printk_info("=================SB 50h=%02x \n", - pci_rawread_config8(PCI_DEV(0, 0x11, 0), 0x50)); + pci_rawread_config8(PCI_RAWDEV(0, 0x11, 0), 0x50));
/* FIXME: Is there a better way to handle this? */ @@ -671,7 +671,7 @@ y = 0; for (; y < 16; y++) { printk_info("%02x ", - pci_rawread_config8(PCI_DEV + pci_rawread_config8(PCI_RAWDEV (0, 0x10, 4), x * 16 + y)); } @@ -690,7 +690,7 @@ y = 0; for (; y < 16; y++) { printk_info("%02x ", - pci_rawread_config8(PCI_DEV + pci_rawread_config8(PCI_RAWDEV (0, 0x10, 4), x * 16 + y)); } @@ -710,7 +710,7 @@ y = 0; for (; y < 16; y++) { printk_info("%02x ", - pci_rawread_config8(PCI_DEV + pci_rawread_config8(PCI_RAWDEV (0, 0x10, 4), x * 16 + y)); } @@ -723,7 +723,7 @@ printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
-// pci_rawwrite_config16(PCI_DEV(0, 0xf, 0), 0xBA, 0x0571); +// pci_rawwrite_config16(PCI_RAWDEV(0, 0xf, 0), 0xBA, 0x0571);
#if 0 x = y = 0; @@ -732,7 +732,7 @@ y = 0; for (; y < 16; y++) { printk_info("%02x ", - pci_rawread_config8(PCI_DEV + pci_rawread_config8(PCI_RAWDEV (0, 0x10, 4), x * 16 + y)); } @@ -743,10 +743,10 @@
#if 0
- y = pci_rawread_config8(PCI_DEV(0, 0xf, 0), 0x0d); + y = pci_rawread_config8(PCI_RAWDEV(0, 0xf, 0), 0x0d); y &= 0x0f; y |= 0x40; - pci_rawwrite_config8(PCI_DEV(0, 0xf, 0), 0x0d, y); + pci_rawwrite_config8(PCI_RAWDEV(0, 0xf, 0), 0x0d, y); #endif
#if 0 @@ -948,41 +948,41 @@ u8 i; /* error form ---- but add the chance to resume for(i=0;i<5;i++){ - pci_rawwrite_config8(PCI_DEV(0, 0, 0), i, d0f0pcitable[i+0xcb]); + pci_rawwrite_config8(PCI_RAWDEV(0, 0, 0), i, d0f0pcitable[i+0xcb]); }
- + */
/* RO reg for(i=0;i<5;i++){ - pci_rawwrite_config8(PCI_DEV(0, 0, 0), i+0xcb, d0f0pcitable[i]); + pci_rawwrite_config8(PCI_RAWDEV(0, 0, 0), i+0xcb, d0f0pcitable[i]); } */
-//boot ok, resume still err in linux +//boot ok, resume still err in linux #if 1 for (i = 0; i < 9; i++) { - pci_rawwrite_config8(PCI_DEV(0, 0, 2), i + 0x50, + pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), i + 0x50, d0f2pcitable[i]); } //9 is warm reset reg, // boot err in coreboot for (i = 10; i < 64; i++) { - pci_rawwrite_config8(PCI_DEV(0, 0, 2), i + 0x50, + pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), i + 0x50, d0f2pcitable[i]); } //0x90 look d0f2 appendixA1 , if set this to 09 or 0b, then some ddr2 will crash. for (i = 65; i < 113; i++) { - pci_rawwrite_config8(PCI_DEV(0, 0, 2), i + 0x50, + pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), i + 0x50, d0f2pcitable[i]); } #endif #ifdef OPTION_1 - pci_rawwrite_config8(PCI_DEV(0, 0, 2), 0x66, 0x09); - pci_rawwrite_config8(PCI_DEV(0, 0, 2), 0x70, 0xdd); - // pci_rawwrite_config8(PCI_DEV(0, 0, 2), 0x90, 0x09); - pci_rawwrite_config8(PCI_DEV(0, 0, 2), 0x92, 0x40); + pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), 0x66, 0x09); + pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), 0x70, 0xdd); + // pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), 0x90, 0x09); + pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), 0x92, 0x40);
#endif
@@ -991,63 +991,63 @@ #if 1
-//d0f3 +//d0f3 /* */ - // pci_rawwrite_config8(PCI_DEV(0, 0, 3), 0x86, 0x3b); setting, my lspci is 0x29 + // pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x86, 0x3b); setting, my lspci is 0x29 //set bit4 cause the ide not be found -// pci_rawwrite_config8(PCI_DEV(0, 0, 3), 0x86, 0x2b); +// pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x86, 0x2b); //set bit1 cause the ide not be found
-// pci_rawwrite_config8(PCI_DEV(0, 0, 3), 0x86, 0x29); - pci_rawwrite_config8(PCI_DEV(0, 0, 3), 0x95, 0x05); - pci_rawwrite_config8(PCI_DEV(0, 0, 3), 0x99, 0x12); +// pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x86, 0x29); + pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x95, 0x05); + pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x99, 0x12);
- pci_rawwrite_config8(PCI_DEV(0, 0, 3), 0xde, 0x00); + pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0xde, 0x00); #endif
-//boot ok, resume err in coreboot +//boot ok, resume err in coreboot #if 1 for (i = 0; i < 99; i++) { - pci_rawwrite_config8(PCI_DEV(0, 0, 4), i + 0x8d, + pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), i + 0x8d, d0f4pcitable[i]); } #endif
#ifdef OPTION_1 - pci_rawwrite_config8(PCI_DEV(0, 0, 4), 0xe9, 0x90); - pci_rawwrite_config8(PCI_DEV(0, 0, 4), 0xec, 0x0); - pci_rawwrite_config8(PCI_DEV(0, 0, 4), 0xed, 0x0); - pci_rawwrite_config8(PCI_DEV(0, 0, 4), 0xee, 0x0); + pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), 0xe9, 0x90); + pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), 0xec, 0x0); + pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), 0xed, 0x0); + pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), 0xee, 0x0); #endif
#if 1 -//boot ok, resume still err in linux +//boot ok, resume still err in linux for (i = 0; i < 160; i++) { - pci_rawwrite_config8(PCI_DEV(0, 0, 5), i + 0x60, + pci_rawwrite_config8(PCI_RAWDEV(0, 0, 5), i + 0x60, d0f5pcitable[i]); } for (i = 0; i < 144; i++) { - pci_rawwrite_config8(PCI_DEV(0, 0, 7), i + 0x60, + pci_rawwrite_config8(PCI_RAWDEV(0, 0, 7), i + 0x60, d0f7pcitable[i]); } for (i = 0; i < 3; i++) { - pci_rawwrite_config8(PCI_DEV(0, 1, 0), i + 0xb0, + pci_rawwrite_config8(PCI_RAWDEV(0, 1, 0), i + 0xb0, d1f0pcitable[i]); } for (i = 0; i < 96; i++) { - pci_rawwrite_config8(PCI_DEV(0, 0xc, 0), i + 0x40, + pci_rawwrite_config8(PCI_RAWDEV(0, 0xc, 0), i + 0x40, dcf0pcitable[i]); } #endif
#ifdef OPTION_1 - pci_rawwrite_config8(PCI_DEV(0, 0, 7), 0x61, 0x0); - pci_rawwrite_config8(PCI_DEV(0, 0, 7), 0x63, 0x0); - pci_rawwrite_config8(PCI_DEV(0, 0, 7), 0x76, 0xd0); - pci_rawwrite_config8(PCI_DEV(0, 0xc, 0), 0x88, 0x81); - pci_rawwrite_config8(PCI_DEV(0, 0xc, 0), 0x89, 0x01); - pci_rawwrite_config8(PCI_DEV(0, 0xc, 0), 0x8A, 0x60); + pci_rawwrite_config8(PCI_RAWDEV(0, 0, 7), 0x61, 0x0); + pci_rawwrite_config8(PCI_RAWDEV(0, 0, 7), 0x63, 0x0); + pci_rawwrite_config8(PCI_RAWDEV(0, 0, 7), 0x76, 0xd0); + pci_rawwrite_config8(PCI_RAWDEV(0, 0xc, 0), 0x88, 0x81); + pci_rawwrite_config8(PCI_RAWDEV(0, 0xc, 0), 0x89, 0x01); + pci_rawwrite_config8(PCI_RAWDEV(0, 0xc, 0), 0x8A, 0x60); #endif
//d15f0 @@ -1057,24 +1057,24 @@
#if 1
- pci_rawwrite_config8(PCI_DEV(0, 0x10, 0), 0x4a, 0xa2); // no affect. - pci_rawwrite_config8(PCI_DEV(0, 0x10, 1), 0x4a, 0xa2); - pci_rawwrite_config8(PCI_DEV(0, 0x10, 2), 0x4a, 0xa2); + pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 0), 0x4a, 0xa2); // no affect. + pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 1), 0x4a, 0xa2); + pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 2), 0x4a, 0xa2);
//boot ok, resume still err in linux, and if disable USB, then all ok // for(i=0;i<48;i++){ for (i = 0; i < 44; i++) { - pci_rawwrite_config8(PCI_DEV(0, 0x10, 4), i + 0x40, + pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 4), i + 0x40, d10f4pcitable[i]); } #endif
//#ifdef NOOPTION_1 #if 0 - pci_rawwrite_config8(PCI_DEV(0, 0x10, 4), 0x6b, 0x01); - pci_rawwrite_config8(PCI_DEV(0, 0x10, 4), 0x6d, 0x00); - pci_rawwrite_config8(PCI_DEV(0, 0x10, 4), 0x6e, 0x08); - pci_rawwrite_config8(PCI_DEV(0, 0x10, 4), 0x6f, 0x80); + pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 4), 0x6b, 0x01); + pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 4), 0x6d, 0x00); + pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 4), 0x6e, 0x08); + pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 4), 0x6f, 0x80); #endif
@@ -1083,171 +1083,171 @@ //before (11.0)is add, s3 resume has already always dead in first resume(more frequenly), and sleep ok // for(i=0;i<192;i++){ for (i = 0; i < 6; i++) { - pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40, + pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, d11f0pcitable[i]); } //6 is uart and dvp vcp, will have // HAVE no com1 ,and no gui show,textmode ok ,s3 sleep ok, resume fail
//7-18 is my familar part - for (i = 7; i < 18; i++) { //sleep ok ,resume sleep err 2 - pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40, + for (i = 7; i < 18; i++) { //sleep ok ,resume sleep err 2 + pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, d11f0pcitable[i]); }
- for (i = 18; i < 21; i++) { //sleep ok , sleep err 1, resume - pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40, + for (i = 18; i < 21; i++) { //sleep ok , sleep err 1, resume + pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, d11f0pcitable[i]); } //0x55 56 57 irq intA#B#C# linkA#linkB#linkC# for (i = 24; i < 27; i++) { //sleep ok , resume sleep err 1 resume 1 - pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40, + pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, d11f0pcitable[i]); } //5b port 80h - pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x5b, 0x0, 0x08); + pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x5b, 0x0, 0x08); // i++; - // pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i+0x40, d11f0pcitable[i]); + // pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i+0x40, d11f0pcitable[i]);
for (i = 28; i < 72; i++) { //sleep ok , resume sleep err 1 , resume 1ci - pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40, + pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, d11f0pcitable[i]); } //7273ACPI BASE
for (i = 74; i < 112; i++) { //boot ok, resume still err in linux - pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40, + pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, d11f0pcitable[i]); }
//B0B4B5 dvp vcp, if copy this ,then no uart, no gui(of unbuntu) - // pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), 0xb0, d11f0pcitable[112]); - i = pci_rawread_config8(PCI_DEV(0, 17, 0), 0xB0); + // pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), 0xb0, d11f0pcitable[112]); + i = pci_rawread_config8(PCI_RAWDEV(0, 17, 0), 0xB0); //multiplex with VCP // i = i | 0x30; i = i & 0xf7; - pci_rawwrite_config8(PCI_DEV(0, 17, 0), 0xB0, i); + pci_rawwrite_config8(PCI_RAWDEV(0, 17, 0), 0xB0, i);
for (i = 113; i < 114; i++) { //boot ok, resume still err in linux - pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40, + pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, d11f0pcitable[i]); }
for (i = 115; i < 116; i++) { //boot ok, resume still err in linux - pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40, + pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, d11f0pcitable[i]); }
for (i = 118; i < 192; i++) { //boot ok, resume still err in linux - pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40, + pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, d11f0pcitable[i]); } #endif #ifdef NOOPTION_1 // for(i=0;i<192;i++){ for (i = 0; i < 6; i++) { - pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40, + pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, OPTION_1_d11f0pcitable[i]); } //6 is uart and dvp vcp, will have // HAVE no com1 ,and no gui show,textmode ok ,s3 sleep ok, resume fail
//7-18 is my familar part for (i = 7; i < 18; i++) { // sleep err 2 - pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40, + pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, OPTION_1_d11f0pcitable[i]); }
for (i = 18; i < 21; i++) { //sleep ok , resume ??? - pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40, + pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, d11f0pcitable[i]); } //0x55 56 57 irq intA#B#C# linkA#linkB#linkC# for (i = 24; i < 27; i++) { //sleep ok , resume ??? - pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40, + pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, d11f0pcitable[i]); } //5b port 80h i++; - pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40, + pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, OPTION_1_d11f0pcitable[i]);
for (i = 28; i < 72; i++) { //sleep ok , resume??? - pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40, + pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, OPTION_1_d11f0pcitable[i]); } //7273ACPI BASE
for (i = 74; i < 112; i++) { //boot ok, resume still err in linux - pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40, + pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, OPTION_1_d11f0pcitable[i]); }
//B0B4B5 dvp vcp, if copy this ,then no uart, no gui(of unbuntu) - // pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), 0xb0, OPTION_1_d11f0pcitable[112]); - i = pci_rawread_config8(PCI_DEV(0, 17, 0), 0xB0); + // pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), 0xb0, OPTION_1_d11f0pcitable[112]); + i = pci_rawread_config8(PCI_RAWDEV(0, 17, 0), 0xB0); //multiplex with VCP // i = i | 0x30; i = i & 0xf7; - pci_rawwrite_config8(PCI_DEV(0, 17, 0), 0xB0, i); + pci_rawwrite_config8(PCI_RAWDEV(0, 17, 0), 0xB0, i);
for (i = 113; i < 114; i++) { //boot ok, resume still err in linux - pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40, + pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, OPTION_1_d11f0pcitable[i]); }
for (i = 115; i < 116; i++) { //boot ok, resume still err in linux - pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40, + pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, OPTION_1_d11f0pcitable[i]); }
for (i = 118; i < 192; i++) { //boot ok, resume still err in linux - pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40, + pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, OPTION_1_d11f0pcitable[i]); } #endif
#if 1 - pci_rawwrite_config16(PCI_DEV(0, 0xf, 0), 0xBA, PCI_DEVICE_ID_VIA_VX855_IDE); //5324 - pci_rawwrite_config16(PCI_DEV(0, 0xf, 0), 0xBE, + pci_rawwrite_config16(PCI_RAWDEV(0, 0xf, 0), 0xBA, PCI_DEVICE_ID_VIA_VX855_IDE); //5324 + pci_rawwrite_config16(PCI_RAWDEV(0, 0xf, 0), 0xBE, PCI_DEVICE_ID_VIA_VX855_IDE); - pci_rawwrite_config16(PCI_DEV(0, 0x11, 0), 0xA0, + pci_rawwrite_config16(PCI_RAWDEV(0, 0x11, 0), 0xA0, PCI_VENDOR_ID_VIA); - pci_rawwrite_config16(PCI_DEV(0, 0x11, 0), 0xA2, PCI_DEVICE_ID_VIA_VX855_LPC); //8353 - i = pci_rawread_config8(PCI_DEV(0, 0x11, 0), 0x79); + pci_rawwrite_config16(PCI_RAWDEV(0, 0x11, 0), 0xA2, PCI_DEVICE_ID_VIA_VX855_LPC); //8353 + i = pci_rawread_config8(PCI_RAWDEV(0, 0x11, 0), 0x79); i &= ~0x40; i |= 0x40; - pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), 0x79, i); - pci_rawwrite_config16(PCI_DEV(0, 0x11, 0), 0x72, + pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), 0x79, i); + pci_rawwrite_config16(PCI_RAWDEV(0, 0x11, 0), 0x72, PCI_DEVICE_ID_VIA_VX855_LPC);
//boot ok, resume still err in linux for (i = 0; i < 192; i++) { - pci_rawwrite_config8(PCI_DEV(0, 0x11, 7), i + 0x40, + pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), i + 0x40, d11f7pcitable[i]); } #endif #ifdef OPTION_1 - pci_rawwrite_config8(PCI_DEV(0, 0x11, 7), 0x61, 0x2a); - pci_rawwrite_config8(PCI_DEV(0, 0x11, 7), 0x63, 0xa0); - pci_rawwrite_config8(PCI_DEV(0, 0x11, 7), 0x64, 0xaa); - pci_rawwrite_config8(PCI_DEV(0, 0x11, 7), 0x84, 0x0); - pci_rawwrite_config8(PCI_DEV(0, 0x11, 7), 0x88, 0x02); - pci_rawwrite_config8(PCI_DEV(0, 0x11, 7), 0xe6, 0x3f); + pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0x61, 0x2a); + pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0x63, 0xa0); + pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0x64, 0xaa); + pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0x84, 0x0); + pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0x88, 0x02); + pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0xe6, 0x3f); #endif
- pci_rawwrite_config8(PCI_DEV(0, 0x14, 0), 0x40, 0x20); - pci_rawwrite_config8(PCI_DEV(0, 0x14, 0), 0x41, 0x31); + pci_rawwrite_config8(PCI_RAWDEV(0, 0x14, 0), 0x40, 0x20); + pci_rawwrite_config8(PCI_RAWDEV(0, 0x14, 0), 0x41, 0x31);
#ifdef OPTION_1 - pci_rawwrite_config8(PCI_DEV(0, 0x14, 0), 0x40, 0x00); + pci_rawwrite_config8(PCI_RAWDEV(0, 0x14, 0), 0x40, 0x00); #endif
@@ -1256,11 +1256,11 @@ u8 i911; //disable CHB L.L //set VGA memory selection - i911 = pci_rawread_config8(PCI_DEV(0, 0x1, 0), 0xb0); + i911 = pci_rawread_config8(PCI_RAWDEV(0, 0x1, 0), 0xb0); i911 &= 0xF8; //ByteVal |= 0x03; i911 |= 0x01; - pci_rawwrite_config8(PCI_DEV(0, 0x1, 0), 0xb0, i911); + pci_rawwrite_config8(PCI_RAWDEV(0, 0x1, 0), 0xb0, i911);
#if 1 @@ -1290,8 +1290,8 @@
- //pci_rawmodify_config8(PCI_DEV(0, 0x10, 4), 0x04, 0x17, 0x17);// -// pci_rawmodify_config8(PCI_DEV(0, 0x10, 4), 0x0c, 0x08, 0xff);/// + //pci_rawmodify_config8(PCI_RAWDEV(0, 0x10, 4), 0x04, 0x17, 0x17);// +// pci_rawmodify_config8(PCI_RAWDEV(0, 0x10, 4), 0x0c, 0x08, 0xff);///
Added: trunk/coreboot-v2/src/northbridge/via/vx800/pci_rawops.h =================================================================== --- trunk/coreboot-v2/src/northbridge/via/vx800/pci_rawops.h (rev 0) +++ trunk/coreboot-v2/src/northbridge/via/vx800/pci_rawops.h 2009-07-07 17:54:26 UTC (rev 4406) @@ -0,0 +1,267 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 One Laptop per Child, Association, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef ARCH_I386_PCI_RAWOPS_H +# define ARCH_I386_PCI_RAWOPS_H 1 +#include <stdint.h> + +#define PCI_RAWDEV(SEGBUS, DEV, FN) ( \ + (((SEGBUS) & 0xFFF) << 20) | \ + (((DEV) & 0x1F) << 15) | \ + (((FN) & 0x07) << 12)) +struct VIA_PCI_REG_INIT_TABLE { + u8 ChipRevisionStart; + u8 ChipRevisionEnd; + u8 Bus; + u8 Device; + u8 Function; + u32 Register; + u8 Mask; + u8 Value; +}; +typedef unsigned device_t_raw; /* pci and pci_mmio need to have different ways to have dev */ + +/* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G, + * We don't need to set %fs, and %gs anymore + * Before that We need to use %gs, and leave %fs to other RAM access + */ + uint8_t pci_io_rawread_config8(device_t_raw dev, unsigned where) +{ + unsigned addr; +#if PCI_IO_CFG_EXT == 0 + addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); //seg == 0 +#endif + outl(0x80000000 | (addr & ~3), 0xCF8); + return inb(0xCFC + (addr & 3)); +} + +#if MMCONF_SUPPORT + uint8_t pci_mmio_rawread_config8(device_t_raw dev, unsigned where) +{ + unsigned addr; + addr = dev | where; + return read8x(addr); +} +#endif + uint8_t pci_rawread_config8(device_t_raw dev, unsigned where) +{ +#if MMCONF_SUPPORT + return pci_mmio_rawread_config8(dev, where); +#else + return pci_io_rawread_config8(dev, where); +#endif +} + + uint16_t pci_io_rawread_config16(device_t_raw dev, unsigned where) +{ + unsigned addr; +#if PCI_IO_CFG_EXT == 0 + addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); +#endif + outl(0x80000000 | (addr & ~3), 0xCF8); + return inw(0xCFC + (addr & 2)); +} + +#if MMCONF_SUPPORT + uint16_t pci_mmio_rawread_config16(device_t_raw dev, unsigned where) +{ + unsigned addr; + addr = dev | where; + return read16x(addr); +} +#endif + + uint16_t pci_rawread_config16(device_t_raw dev, unsigned where) +{ +#if MMCONF_SUPPORT + return pci_mmio_rawread_config16(dev, where); +#else + return pci_io_rawread_config16(dev, where); +#endif +} + + + uint32_t pci_io_rawread_config32(device_t_raw dev, unsigned where) +{ + unsigned addr; +#if PCI_IO_CFG_EXT == 0 + addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); +#endif + outl(0x80000000 | (addr & ~3), 0xCF8); + return inl(0xCFC); +} + +#if MMCONF_SUPPORT + uint32_t pci_mmio_rawread_config32(device_t_raw dev, unsigned where) +{ + unsigned addr; + addr = dev | where; + return read32x(addr); +} +#endif + + uint32_t pci_rawread_config32(device_t_raw dev, unsigned where) +{ +#if MMCONF_SUPPORT + return pci_mmio_rawread_config32(dev, where); +#else + return pci_io_rawread_config32(dev, where); +#endif +} + + void pci_io_rawwrite_config8(device_t_raw dev, unsigned where, uint8_t value) +{ + unsigned addr; +#if PCI_IO_CFG_EXT == 0 + addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); +#endif + outl(0x80000000 | (addr & ~3), 0xCF8); + outb(value, 0xCFC + (addr & 3)); +} + +#if MMCONF_SUPPORT + void pci_mmio_rawwrite_config8(device_t_raw dev, unsigned where, uint8_t value) +{ + unsigned addr; + addr = dev | where; + write8x(addr, value); +} +#endif + + void pci_rawwrite_config8(device_t_raw dev, unsigned where, uint8_t value) +{ +#if MMCONF_SUPPORT + pci_mmio_rawwrite_config8(dev, where, value); +#else + pci_io_rawwrite_config8(dev, where, value); +#endif +} + + + void pci_io_rawwrite_config16(device_t_raw dev, unsigned where, uint16_t value) +{ + unsigned addr; +#if PCI_IO_CFG_EXT == 0 + addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); +#endif + outl(0x80000000 | (addr & ~3), 0xCF8); + outw(value, 0xCFC + (addr & 2)); +} + +#if MMCONF_SUPPORT + void pci_mmio_rawwrite_config16(device_t_raw dev, unsigned where, uint16_t value) +{ + unsigned addr; + addr = dev | where; + write16x(addr, value); +} +#endif + + void pci_rawwrite_config16(device_t_raw dev, unsigned where, uint16_t value) +{ +#if MMCONF_SUPPORT + pci_mmio_rawwrite_config16(dev, where, value); +#else + pci_io_rawwrite_config16(dev, where, value); +#endif +} + + + void pci_io_rawwrite_config32(device_t_raw dev, unsigned where, uint32_t value) +{ + unsigned addr; +#if PCI_IO_CFG_EXT == 0 + addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); +#endif + outl(0x80000000 | (addr & ~3), 0xCF8); + outl(value, 0xCFC); +} + +#if MMCONF_SUPPORT + void pci_mmio_rawwrite_config32(device_t_raw dev, unsigned where, uint32_t value) +{ + unsigned addr; + addr = dev | where; + write32x(addr, value); +} +#endif + + void pci_rawwrite_config32(device_t_raw dev, unsigned where, uint32_t value) +{ +#if MMCONF_SUPPORT + pci_mmio_rawwrite_config32(dev, where, value); +#else + pci_io_rawwrite_config32(dev, where, value); +#endif +} + + +void pci_rawmodify_config8(device_t_raw dev, unsigned where, u8 orval,u8 mask) +{ u8 data=pci_rawread_config8(dev,where); + data&=(~mask); + data|=orval; + pci_rawwrite_config8(dev,where,data); +} +void pci_rawmodify_config16(device_t_raw dev, unsigned where, uint16_t orval,uint16_t mask) +{ uint16_t data=pci_rawread_config16(dev,where); + data&=(~mask); + data|=orval; + pci_rawwrite_config16(dev,where,data); +} +void pci_rawmodify_config32(device_t_raw dev, unsigned where, uint32_t orval,uint32_t mask) +{ uint32_t data=pci_rawread_config32(dev,where); + data&=(~mask); + data|=orval; + pci_rawwrite_config32(dev,where,data); +} + +void io_rawmodify_config8(u16 where, uint8_t orval,uint8_t mask) +{ + u8 data=inb(where); + data&=(~mask); + data|=orval; + outb(data,where); +} + +void via_pci_inittable(u8 chipversion,struct VIA_PCI_REG_INIT_TABLE* initdata) +{ + u8 i=0; + device_t_raw devbxdxfx; + for(i=0;;i++) { + if((initdata[i].Mask==0)&&(initdata[i].Value==0)&&(initdata[i].Bus==0)&&(initdata[i].ChipRevisionEnd==0xff)&&(initdata[i].ChipRevisionStart==0)&&(initdata[i].Device==0)&&(initdata[i].Function==0)&&(initdata[i].Register==0)) + break; + if((chipversion>=initdata[i].ChipRevisionStart)&&(chipversion<=initdata[i].ChipRevisionEnd)){ + devbxdxfx=PCI_RAWDEV(initdata[i].Bus,initdata[i].Device,initdata[i].Function); + pci_rawmodify_config8(devbxdxfx, initdata[i].Register,initdata[i].Value,initdata[i].Mask); + } + } +} +#endif
Modified: trunk/coreboot-v2/src/northbridge/via/vx800/uma_ram_setting.c =================================================================== --- trunk/coreboot-v2/src/northbridge/via/vx800/uma_ram_setting.c 2009-07-07 16:15:43 UTC (rev 4405) +++ trunk/coreboot-v2/src/northbridge/via/vx800/uma_ram_setting.c 2009-07-07 17:54:26 UTC (rev 4406) @@ -173,10 +173,10 @@ pci_write_config32(vga_dev, 0x14, Tmp);
//enable direct cpu frame buffer access - i = pci_conf1_read8(PCI_DEV(0, 0, 3), 0xa1); + i = pci_rawread_config8(PCI_RAWDEV(0, 0, 3), 0xa1); i = (i & 0xf0) | (VIACONFIG_VGA_PCI_10 >> 28); - pci_conf1_write8(PCI_DEV(0, 0, 3), 0xa1, i); - pci_conf1_write8(PCI_DEV(0, 0, 3), 0xa0, 0x01); + pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0xa1, i); + pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0xa0, 0x01);
//enable GFx memory space access control for S.L and mmio ByteVal = pci_read_config8(d0f0_dev, 0xD4);
Copied: trunk/coreboot-v2/targets/via/epia-m700/Config-abuild.lb (from rev 4403, trunk/coreboot-v2/targets/via/epia-m700/Config.lb) =================================================================== --- trunk/coreboot-v2/targets/via/epia-m700/Config-abuild.lb (rev 0) +++ trunk/coreboot-v2/targets/via/epia-m700/Config-abuild.lb 2009-07-07 17:54:26 UTC (rev 4406) @@ -0,0 +1,36 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann uwe@hermann-uwe.de +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +target VENDOR_MAINBOARD +mainboard VENDOR/MAINBOARD + +option CC="CROSSCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option HOSTCC="CROSS_HOSTCC" + +__COMPRESSION__ +__LOGLEVEL__ + +romimage "image" + option COREBOOT_EXTRA_VERSION = "-epia-m700" + payload __PAYLOAD__ +end + +buildrom ./coreboot.rom CONFIG_ROM_SIZE "image"
Property changes on: trunk/coreboot-v2/targets/via/epia-m700/Config-abuild.lb ___________________________________________________________________ Added: svn:mergeinfo +