PCI: 00:15.0 init
PCI: 00:15.0 init finished in 0 msecs
PCI: 00:15.1 init
PCI: 00:15.1 init finished in 0 msecs
PCI: 00:18.1 init
PCI: 00:18.1 init finished in 0 msecs
Note that there is no init for 15.2 above. I
don't know why, if it's
enabled in the mainboard devicetree file.
15.2 is a PCIe root port, so it is
natural that there is no init for it,
if the endpoint device isn't detected. There won't be PCIe root port
because AGESA hides it, if endpoint is not detected.
Another thought - have you compared PCI bus numbers
between vendor BIOS and coreboot? They can change around, certainly
bus numbers but wasn't there a thread a while back with addresses
being confused too?
This is another thing that can be customized. Each mainboard
OemCustomize.c file which defines an array of type
PCIe_PORT_DESCRIPTOR., the 3rd (and 4th on some families) parameter in
PCIE_PORT_DATA_INITIALIZER indicate the device number that will be
assigned to the PCIe engines (lanes). So you can freely route the ports
to device numbers.
Sorry I can't suggest anything more concrete
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