Hi,
I've a reboot loop on master on the Thinkpad X200.
It's configured to run without the Management Engine firmware (which is not present on the flash chip).
Here's the boot log:
coreboot-4.10-678-gdd12d53494b-dirty Mon Sep 16 13:42:10 UTC 2019 romstage starting (log level: 8)... WARNING: Ignoring S4-assertion-width violation. Stepping B3 2 CPU cores AMT enabled capable of DDR2 of 800 MHz or lower VT-d enabled GMCH: GM45 TXT enabled Render frequency: 533 MHz IGD enabled PCIe-to-GMCH enabled GMCH supports DDR3 with 1067 MT or less GMCH supports FSB with up to 1067 MHz SMBus controller enabled. 0:50:b 2:51:b DDR mask 5, DDR 3 Bank 0 populated: Raw card type: F Row addr bits: 14 Col addr bits: 10 byte width: 1 page size: 1024 banks: 8 ranks: 2 tAAmin: 105 tCKmin: 15 Max clock: 533 MHz CAS: 0x01c0 Bank 1 populated: Raw card type: F Row addr bits: 14 Col addr bits: 10 byte width: 1 page size: 1024 banks: 8 ranks: 2 tAAmin: 105 tCKmin: 15 Max clock: 533 MHz CAS: 0x01e0 Trying CAS 7, tCK 15. Found compatible clock / CAS pair: 533 / 7. Timing values: tCLK: 15 tRAS: 20 tRP: 7 tRCD: 7 tRFC: 68 tWR: 8 tRD: 11 tRRD: 4 tFAW: 20 tWL: 6 Changing memory frequency: old 3, new 6. Setting IGD memory frequencies for VCO #1. Memory configured in dual-channel assymetric mode. Memory map: TOM = 512MB TOLUD = 512MB TOUUD = 512MB REMAP: base = 65535MB limit = 0MB usedMEsize: 0MB JEDEC init @0x00000000 JEDEC init @0x08000000 JEDEC init @0x10000000 JEDEC init @0x18000000 Final timings for group 0, ch 0: 6.1.0.5.6 Final timings for group 1, ch 0: 6.0.2.8.4 Final timings for group 2, ch 0: 6.1.2.3.4 Final timings for group 3, ch 0: 6.1.0.8.6 Final timings for group 0, ch 1: 6.1.0.3.5 Final timings for group 1, ch 1: 6.0.2.6.1 Final timings for group 2, ch 1: 6.1.2.1.6 Final timings for group 3, ch 1: 6.1.0.8.1 Lower bound for byte lane 0, ch 0: 0.0 Upper bound for byte lane 0, ch 0: 10.6 Final timings for byte lane 0, ch 0: 5.3 Lower bound for byte lane 1, ch 0: 0.0 Upper bound for byte lane 1, ch 0: 9.7 Final timings for byte lane 1, ch 0: 4.7 Lower bound for byte lane 2, ch 0: 0.0 Upper bound for byte lane 2, ch 0: 9.4 Final timings for byte lane 2, ch 0: 4.6 Lower bound for byte lane 3, ch 0: 0.0 Upper bound for byte lane 3, ch 0: 10.2 Final timings for byte lane 3, ch 0: 5.1 Lower bound for byte lane 4, ch 0: 0.0 Upper bound for byte lane 4, ch 0: 9.2 Final timings for byte lane 4, ch 0: 4.5 Lower bound for byte lane 5, ch 0: 0.0 Upper bound for byte lane 5, ch 0: 7.7 Final timings for byte lane 5, ch 0: 3.7 Lower bound for byte lane 6, ch 0: 0.0 Upper bound for byte lane 6, ch 0: 8.5 Final timings for byte lane 6, ch 0: 4.2 Lower bound for byte lane 7, ch 0: 0.0 Upper bound for byte lane 7, ch 0: 10.5 Final timings for byte lane 7, ch 0: 5.2 Lower bound for byte lane 0, ch 1: 0.0 Upper bound for byte lane 0, ch 1: 10.1 Final timings for byte lane 0, ch 1: 5.0 Lower bound for byte lane 1, ch 1: 0.0 Upper bound for byte lane 1, ch 1: 11.6 Final timings for byte lane 1, ch 1: 5.7 Lower bound for byte lane 2, ch 1: 0.0 Upper bound for byte lane 2, ch 1: 11.6 Final timings for byte lane 2, ch 1: 5.7 Lower bound for byte lane 3, ch 1: 0.0 Upper bound for byte lane 3, ch 1: 9.6 Final timings for byte lane 3, ch 1: 4.7 Lower bound for byte lane 4, ch 1: 0.0 Upper bound for byte lane 4, ch 1: 10.6 Final timings for byte lane 4, ch 1: 5.3 Lower bound for byte lane 5, ch 1: 0.0 Upper bound for byte lane 5, ch 1: 9.3 Final timings for byte lane 5, ch 1: 4.5 Lower bound for byte lane 6, ch 1: 0.0 Upper bound for byte lane 6, ch 1: 8.5 Final timings for byte lane 6, ch 1: 4.2 Lower bound for byte lane 7, ch 1: 0.0 Upper bound for byte lane 7, ch 1: 10.7 Final timings for byte lane 7, ch 1: 5.3 Lower bound for group 0, ch 0: 1.6.3 Upper bound for group 0, ch 0: 2.3.1 Final timings for group 0, ch 0: 1.10.6 Lower bound for group 1, ch 0: 1.6.1 Upper bound for group 1, ch 0: 2.2.3 Final timings for group 1, ch 0: 1.10.2 Lower bound for group 2, ch 0: 2.0.0 Upper bound for group 2, ch 0: 2.10.0 Final timings for group 2, ch 0: 2.5.0 Lower bound for group 3, ch 0: 2.4.7 Upper bound for group 3, ch 0: 3.1.0 Final timings for group 3, ch 0: 2.8.7 FMAP: Found "FLASH" version 1.1 at 10000. FMAP: base = ff800000 size = 800000 #areas = 3 FMAP: area COREBOOT found @ 10200 (8322560 bytes) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 30200 size 680 IGD decoded, subtracting 32M UMA and 4M GTT Memory configured in dual-channel interleaved mode. Memory map: TOM = 4096MB TOLUD = 2048MB TOUUD = 6144MB REMAP: base = 4096MB limit = 6080MB usedMEsize: 0MB Enabling IGD. Finally disabling PEG in favor of IGD. PEG x1 disabled, SDVO disabled ICH9 waits for VC1 negotiation... done. ICH9 waits for port arbitration table update... done. CBMEM: IMD: root @ 7d7ff000 254 entries. IMD: root @ 7d7fec00 62 entries. External stage cache: IMD: root @ 7dbff000 254 entries. IMD: root @ 7dbfec00 62 entries. exit main() SMM Memory Map SMRAM : 0x7da00000 0x200000 Subregion 0: 0x7da00000 0x100000 Subregion 1: 0x7db00000 0x100000 Subregion 2: 0x7dc00000 0x0 MTRR Range: Start=7d000000 End=7d800000 (Size 800000) MTRR Range: Start=7da00000 End=7dc00000 (Size 200000) MTRR Range: Start=ff800000 End=0 (Size 800000) CBFS @ 10200 size 7efe00 CBFS: 'Master Header Locator' located CBFS at [10200:800000) CBFS: Locating 'fallback/postcar' CBFS: Found @ offset 308c0 size 4aac Decompressing stage fallback/postcar @ 0x7d7d2fc0 (35632 bytes) Loading module at 7d7d3000 with entry 7d7d3000. filesize: 0x47d0 memsize: 0x8af0 Processing 160 relocs. Offset value of 0x7b7d3000 usbdebug: postcar starting... CBFS @ 10200 size 7efe00 CBFS: 'Master Header Locator' located CBFS at [10200:800000) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset e640 size 1a9c8 Decompressing stage fallback/ramstage @ 0x7d78bfc0 (282896 bytes) Loading module at 7d78c000 with entry 7d78c000. filesize: 0x36cd0 memsize: 0x450d0 Processing 3881 relocs. Offset value of 0x7c98c000 usbdebug: ramstage starting... Normal boot. apic timer freq (266) may be too fast. BS: BS_PRE_DEVICE times (us): entry 0 run 0 exit 0 Initializing i82801ix southbridge... BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 20995 exit 0 Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 DOMAIN: 0000: enabled 1 APIC: 00: enabled 1 APIC: acac: enabled 0 PCI: 00:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:03.0: enabled 1 PCI: 00:03.1: enabled 0 PCI: 00:03.2: enabled 0 PCI: 00:03.3: enabled 0 PCI: 00:19.0: enabled 1 PCI: 00:1a.0: enabled 1 PCI: 00:1a.1: enabled 1 PCI: 00:1a.2: enabled 1 PCI: 00:1a.7: enabled 1 PCI: 00:1b.0: enabled 1 PCI: 00:1c.0: enabled 1 PCI: 00:1c.1: enabled 1 PCI: 00:1c.2: enabled 1 PCI: 00:1c.3: enabled 1 PCI: 00:1c.4: enabled 0 PCI: 00:1c.5: enabled 0 PCI: 00:1d.0: enabled 1 PCI: 00:1d.1: enabled 1 PCI: 00:1d.2: enabled 1 PCI: 00:1d.7: enabled 1 PCI: 00:1e.0: enabled 1 PCI: 00:1f.0: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 1 PCI: 00:1f.5: enabled 0 PCI: 00:1f.6: enabled 0 IOAPIC: 02: enabled 1 PNP: 00ff.1: enabled 1 PNP: 00ff.2: enabled 1 PNP: 164e.3: enabled 1 PNP: 164e.2: enabled 0 PNP: 164e.7: enabled 0 PNP: 164e.19: enabled 0 I2C: 00:54: enabled 1 I2C: 00:55: enabled 1 I2C: 00:56: enabled 1 I2C: 00:57: enabled 1 I2C: 00:5c: enabled 1 I2C: 00:5d: enabled 1 I2C: 00:5e: enabled 1 I2C: 00:5f: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 APIC: acac: enabled 0 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:03.0: enabled 1 PCI: 00:03.1: enabled 0 PCI: 00:03.2: enabled 0 PCI: 00:03.3: enabled 0 PCI: 00:19.0: enabled 1 PCI: 00:1a.0: enabled 1 PCI: 00:1a.1: enabled 1 PCI: 00:1a.2: enabled 1 PCI: 00:1a.7: enabled 1 PCI: 00:1b.0: enabled 1 PCI: 00:1c.0: enabled 1 PCI: 00:1c.1: enabled 1 PCI: 00:1c.2: enabled 1 PCI: 00:1c.3: enabled 1 PCI: 00:1c.4: enabled 0 PCI: 00:1c.5: enabled 0 PCI: 00:1d.0: enabled 1 PCI: 00:1d.1: enabled 1 PCI: 00:1d.2: enabled 1 PCI: 00:1d.7: enabled 1 PCI: 00:1e.0: enabled 1 PCI: 00:1f.0: enabled 1 IOAPIC: 02: enabled 1 PNP: 00ff.1: enabled 1 PNP: 00ff.2: enabled 1 PNP: 164e.3: enabled 1 PNP: 164e.2: enabled 0 PNP: 164e.7: enabled 0 PNP: 164e.19: enabled 0 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 1 I2C: 00:54: enabled 1 I2C: 00:55: enabled 1 I2C: 00:56: enabled 1 I2C: 00:57: enabled 1 I2C: 00:5c: enabled 1 I2C: 00:5d: enabled 1 I2C: 00:5e: enabled 1 I2C: 00:5f: enabled 1 PCI: 00:1f.5: enabled 0 PCI: 00:1f.6: enabled 0 Root Device scanning... root_dev_scan_bus for Root Device CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/2a40] enabled PCI: 00:02.0 [8086/0000] ops PCI: 00:02.0 [8086/2a42] enabled PCI: 00:02.1 [8086/2a43] enabled PCI: Static device PCI: 00:03.0 not found, disabling it. PCI: 00:19.0 [8086/10f5] enabled PCI: 00:1a.0 [8086/2937] enabled PCI: 00:1a.1 [8086/2938] enabled PCI: 00:1a.2 [8086/2939] enabled PCI: 00:1a.7 [8086/0000] ops PCI: 00:1a.7 [8086/293c] enabled PCI: 00:1b.0 [8086/293e] ops PCI: 00:1b.0 [8086/293e] enabled PCI: 00:1c.0 [8086/0000] bus ops PCI: 00:1c.0 [8086/2940] enabled PCI: 00:1c.1 [8086/0000] bus ops PCI: 00:1c.1 [8086/2942] enabled PCI: 00:1c.2 [8086/0000] bus ops PCI: 00:1c.2 [8086/2944] enabled PCI: 00:1c.3 [8086/0000] bus ops PCI: 00:1c.3 [8086/2946] enabled PCI: 00:1d.0 [8086/2934] enabled PCI: 00:1d.1 [8086/2935] enabled PCI: 00:1d.2 [8086/2936] enabled PCI: 00:1d.7 [8086/0000] ops PCI: 00:1d.7 [8086/293a] enabled PCI: 00:1e.0 [8086/0000] bus ops PCI: 00:1e.0 [8086/2448] enabled PCI: 00:1f.0 [8086/0000] bus ops PCI: 00:1f.0 [8086/2917] enabled PCI: 00:1f.2 [8086/0000] ops FMAP: area COREBOOT found @ 10200 (8322560 bytes) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 30200 size 680 PCI: 00:1f.2 [8086/2928] enabled PCI: 00:1f.3 [8086/0000] bus ops PCI: 00:1f.3 [8086/2930] enabled PCI: Leftover static devices: PCI: 00:03.0 PCI: 00:03.1 PCI: 00:03.2 PCI: 00:03.3 PCI: 00:1c.4 PCI: 00:1c.5 PCI: 00:1f.5 PCI: 00:1f.6 PCI: Check your devicetree.cb. PCI: 00:1c.0 scanning... do_pci_scan_bridge for PCI: 00:1c.0 PCI: pci_scan_bus for bus 01 scan_bus: scanning of bus PCI: 00:1c.0 took 22707 usecs PCI: 00:1c.1 scanning... do_pci_scan_bridge for PCI: 00:1c.1 PCI: pci_scan_bus for bus 02 PCI: 02:00.0 [168c/002a] enabled Enabling Common Clock Configuration PCIE CLK PM is not supported by endpoint ASPM: Enabled L1 Failed to enable LTR for dev = PCI: 02:00.0 scan_bus: scanning of bus PCI: 00:1c.1 took 66042 usecs PCI: 00:1c.2 scanning... do_pci_scan_bridge for PCI: 00:1c.2 PCI: pci_scan_bus for bus 03 scan_bus: scanning of bus PCI: 00:1c.2 took 26591 usecs PCI: 00:1c.3 scanning... do_pci_scan_bridge for PCI: 00:1c.3 PCI: pci_scan_bus for bus 04 scan_bus: scanning of bus PCI: 00:1c.3 took 27092 usecs PCI: 00:1e.0 scanning... do_pci_scan_bridge for PCI: 00:1e.0 PCI: pci_scan_bus for bus 05 scan_bus: scanning of bus PCI: 00:1e.0 took 27356 usecs PCI: 00:1f.0 scanning... scan_lpc_bus for PCI: 00:1f.0 IOAPIC: 02 enabled FMAP: area COREBOOT found @ 10200 (8322560 bytes) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 30200 size 680 No CMOS option 'touchpad'. FMAP: area COREBOOT found @ 10200 (8322560 bytes) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 30200 size 680 PMH7: ID 03 Revision 10 PNP: 00ff.1 enabled Clearing EC output queue... EC output queue has been cleared. recv_ec_data: 0x37 recv_ec_data: 0x58 recv_ec_data: 0x48 recv_ec_data: 0x54 recv_ec_data: 0x32 recv_ec_data: 0x32 recv_ec_data: 0x57 recv_ec_data: 0x57 recv_ec_data: 0x06 recv_ec_data: 0x03 recv_ec_data: 0x40 recv_ec_data: 0x10 EC Firmware ID 7XHT22WW-3.6, Version 4.01A FMAP: area COREBOOT found @ 10200 (8322560 bytes) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 30200 size 680 FMAP: area COREBOOT found @ 10200 (8322560 bytes) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 30200 size 680 FMAP: area COREBOOT found @ 10200 (8322560 bytes) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 30200 size 680 No CMOS option 'usb_always_on'. recv_ec_data: 0x00 FMAP: area COREBOOT found @ 10200 (8322560 bytes) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 30200 size 680 recv_ec_data: 0x00 recv_ec_data: 0x10 FMAP: area COREBOOT found @ 10200 (8322560 bytes) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 30200 size 680 FMAP: area COREBOOT found @ 10200 (8322560 bytes) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 30200 size 680 recv_ec_data: 0x20 H8: WWAN detection not implemented. Assuming WWAN installed FMAP: area COREBOOT found @ 10200 (8322560 bytes) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 30200 size 680 recv_ec_data: 0x30 FMAP: area COREBOOT found @ 10200 (8322560 bytes) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 30200 size 680 recv_ec_data: 0x00 FMAP: area COREBOOT found @ 10200 (8322560 bytes) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 30200 size 680 recv_ec_data: 0x00 FMAP: area COREBOOT found @ 10200 (8322560 bytes) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 30200 size 680 recv_ec_data: 0xa6 FMAP: area COREBOOT found @ 10200 (8322560 bytes) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 30200 size 680 recv_ec_data: 0xa6 recv_ec_data: 0x70 dock is connected recv_ec_data: 0xa0 PNP: 00ff.2 enabled PNP: 164e.3 enabled PNP: 164e.2 disabled PNP: 164e.7 disabled PNP: 164e.19 disabled scan_lpc_bus for PCI: 00:1f.0 done scan_bus: scanning of bus PCI: 00:1f.0 took 748272 usecs PCI: 00:1f.3 scanning... scan_generic_bus for PCI: 00:1f.3 bus: PCI: 00:1f.3[0]-> I2C: 01:54 enabled bus: PCI: 00:1f.3[0]-> I2C: 01:55 enabled bus: PCI: 00:1f.3[0]-> I2C: 01:56 enabled bus: PCI: 00:1f.3[0]-> I2C: 01:57 enabled bus: PCI: 00:1f.3[0]-> USB
coreboot-4.10-678-gdd12d53494b-dirty Mon Sep 16 13:42:10 UTC 2019 romstage starting (log level: 8)... Stepping B3
Denis.