Author: uwe Date: 2007-12-03 21:32:53 +0100 (Mon, 03 Dec 2007) New Revision: 534
Added: LinuxBIOSv3/include/northbridgelib.h LinuxBIOSv3/lib/northbridgelib.c Modified: LinuxBIOSv3/arch/x86/Makefile LinuxBIOSv3/northbridge/amd/geodelx/geodelx.c LinuxBIOSv3/northbridge/intel/i440bxemulation/i440bx.c Log: Factor out common functions which almost all northbridges share into lib/northbridgelib.c.
Signed-off-by: Uwe Hermann uwe@hermann-uwe.de Acked-by: Ronald G. Minnich rminnich@gmail.com
Modified: LinuxBIOSv3/arch/x86/Makefile =================================================================== --- LinuxBIOSv3/arch/x86/Makefile 2007-11-30 22:43:42 UTC (rev 533) +++ LinuxBIOSv3/arch/x86/Makefile 2007-12-03 20:32:53 UTC (rev 534) @@ -172,7 +172,7 @@ #
STAGE2_LIB_OBJ = stage2.o clog2.o mem.o tables.o delay.o \ - compute_ip_checksum.o string.o + compute_ip_checksum.o string.o northbridgelib.o
STAGE2_ARCH_X86_OBJ = archtables.o linuxbios_table.o udelay_io.o STAGE2_ARCH_X86_OBJ += pci_ops_auto.o pci_ops_conf1.o pci_ops_conf2.o
Added: LinuxBIOSv3/include/northbridgelib.h =================================================================== --- LinuxBIOSv3/include/northbridgelib.h (rev 0) +++ LinuxBIOSv3/include/northbridgelib.h 2007-12-03 20:32:53 UTC (rev 534) @@ -0,0 +1,26 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> + +void pci_domain_read_resources(struct device *dev); +void ram_resource(struct device *dev, unsigned long index, + unsigned long basek, unsigned long sizek); +unsigned int pci_domain_scan_bus(struct device *dev, unsigned int max);
Added: LinuxBIOSv3/lib/northbridgelib.c =================================================================== --- LinuxBIOSv3/lib/northbridgelib.c (rev 0) +++ LinuxBIOSv3/lib/northbridgelib.c 2007-12-03 20:32:53 UTC (rev 534) @@ -0,0 +1,92 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <console.h> +#include <device/device.h> +#include <device/pci.h> + +/** + * Set resources for the PCI domain. + * + * A PCI domain contains the I/O and memory resource address space below it. + * Set up basic global ranges for I/O and memory. Allocation of sub-resources + * draws on these top-level resources in the usual hierarchical manner. + * + * @param dev The northbridge device. + */ +void pci_domain_read_resources(struct device *dev) +{ + struct resource *res; + + /* Initialize the system-wide I/O space constraints. */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + res->limit = 0xffffUL; + res->flags = + IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + + /* Initialize the system-wide memory resources constraints. */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res->limit = 0xffffffffULL; + res->flags = + IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; +} + +/** + * Create a RAM resource, by taking the passed-in size and creating + * a resource record. + * + * @param dev The device. + * @param index A resource index. + * @param basek Base memory address in KB. + * @param sizek Size of memory in KB. + */ +void ram_resource(struct device *dev, unsigned long index, + unsigned long basek, unsigned long sizek) +{ + struct resource *res; + + if (!sizek) + return; + + res = new_resource(dev, index); + res->base = ((resource_t) basek) << 10; /* Convert to bytes. */ + res->size = ((resource_t) sizek) << 10; /* Convert to bytes. */ + res->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + printk(BIOS_SPEW, "Adding RAM resource (%lld bytes)\n", res->size); +} + +/** + * Support for scan bus from the "tippy top" -- i.e. the PCI domain, + * not the 0:0.0 device. + * + * This function works for almost all chipsets (AMD K8 is the exception). + * + * @param dev The PCI domain device. + * @param max Maximum number of devices to scan. + * @return TODO + */ +unsigned int pci_domain_scan_bus(struct device *dev, unsigned int max) +{ + /* There is only one link on this device, and it is always link 0. */ + return pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); +}
Modified: LinuxBIOSv3/northbridge/amd/geodelx/geodelx.c =================================================================== --- LinuxBIOSv3/northbridge/amd/geodelx/geodelx.c 2007-11-30 22:43:42 UTC (rev 533) +++ LinuxBIOSv3/northbridge/amd/geodelx/geodelx.c 2007-12-03 20:32:53 UTC (rev 534) @@ -25,6 +25,7 @@ #include <device/pci_ids.h> #include <msr.h> #include <amd_geodelx.h> +#include <northbridgelib.h>
/* Function prototypes */ extern void chipsetinit(void); @@ -270,58 +271,6 @@ }
/** - * Set resources for the PCI domain. - * - * Just set up basic global ranges for I/O and memory. Allocation of - * sub-resources draws on these top-level resources in the usual - * hierarchical manner. - * - * @param dev The nortbridge device. - */ -static void geodelx_pci_domain_read_resources(struct device *dev) -{ - struct resource *resource; - - printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__); - - /* Initialize the system wide I/O space constraints. */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - resource->limit = 0xffffUL; - resource->flags = - IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - - /* Initialize the system wide memory resources constraints. */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - resource->limit = 0xffffffffULL; - resource->flags = - IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; -} - -/** - * Create a RAM resource, by taking the passed-in size and creating - * a resource record. - * - * @param dev The device. - * @param index A resource index. - * @param basek Base memory address in KB. - * @param sizek Size of memory in KB. - */ -static void ram_resource(struct device *dev, unsigned long index, - unsigned long basek, unsigned long sizek) -{ - struct resource *resource; - - if (!sizek) - return; - - resource = new_resource(dev, index); - resource->base = ((resource_t) basek) << 10; - resource->size = ((resource_t) sizek) << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - -/** * Set resources in the PCI domain. * * Also, as a side effect, create a RAM resource in the child which, @@ -386,21 +335,6 @@ }
/** - * Support for scan bus from the "tippy top" -- i.e. the PCI domain, - * not the 0:0.0 device. - * - * @param dev The PCI domain device. - * @param max Maximum number of devices to scan. - * @return TODO - */ -static unsigned int geodelx_pci_domain_scan_bus(struct device *dev, - unsigned int max) -{ - printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__); - return pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); -} - -/** * Support for APIC cluster init. * * TODO: Should we do this in phase 2? It is now done in phase 6. @@ -426,8 +360,8 @@ static struct device_operations geodelx_pcidomain_ops = { .constructor = default_device_constructor, .phase2_setup_scan_bus = geodelx_pci_domain_phase2, - .phase3_scan = geodelx_pci_domain_scan_bus, - .phase4_read_resources = geodelx_pci_domain_read_resources, + .phase3_scan = pci_domain_scan_bus, + .phase4_read_resources = pci_domain_read_resources, .phase4_set_resources = geodelx_pci_domain_set_resources, .phase5_enable_resources = enable_childrens_resources, .phase6_init = 0, @@ -448,8 +382,8 @@ /** Operations for when the northbridge is running a PCI device. */ static struct device_operations geodelx_pci_ops = { .constructor = default_device_constructor, - .phase3_scan = geodelx_pci_domain_scan_bus, - .phase4_read_resources = geodelx_pci_domain_read_resources, + .phase3_scan = pci_domain_scan_bus, + .phase4_read_resources = pci_domain_read_resources, .phase4_set_resources = geodelx_northbridge_set_resources, .phase5_enable_resources = enable_childrens_resources, .phase6_init = geodelx_northbridge_init,
Modified: LinuxBIOSv3/northbridge/intel/i440bxemulation/i440bx.c =================================================================== --- LinuxBIOSv3/northbridge/intel/i440bxemulation/i440bx.c 2007-11-30 22:43:42 UTC (rev 533) +++ LinuxBIOSv3/northbridge/intel/i440bxemulation/i440bx.c 2007-12-03 20:32:53 UTC (rev 534) @@ -43,46 +43,12 @@ #include <device/device.h> #include <device/pci.h> #include <string.h> +#include <northbridgelib.h> #include "i440bx.h" #include "statictree.h"
/* Here are the ops for 440BX as a PCI domain. */ -/* A PCI domain contains the I/O and memory resource address space below it. */
-static void pci_domain_read_resources(struct device *dev) -{ - struct resource *resource; - - /* Initialize the system wide I/O space constraints. */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - resource->limit = 0xffffUL; - resource->flags = - IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - - /* Initialize the system wide memory resources constraints. */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - resource->limit = 0xffffffffULL; - resource->flags = - IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; -} - -static void ram_resource(struct device *dev, unsigned long index, - unsigned long basek, unsigned long sizek) -{ - struct resource *resource; - - if (!sizek) { - return; - } - resource = new_resource(dev, index); - resource->base = ((resource_t) basek) << 10; - resource->size = ((resource_t) sizek) << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - printk(BIOS_DEBUG, "%s: add ram resource %lld bytes\n", __func__, - resource->size); -} - static void pci_domain_set_resources(struct device *dev) { struct device *mc_dev; @@ -99,13 +65,6 @@ phase4_assign_resources(&dev->link[0]); }
-static unsigned int pci_domain_scan_bus(struct device *dev, unsigned int max) -{ - /* There is only one link on this device, and it is always link 0. */ - max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); - return max; -} - /* Here are the operations for when the northbridge is running a PCI domain. */ /* See mainboard/emulation/qemu-x86 for an example of how these are used. */ struct device_operations i440bxemulation_pcidomainops = {