On Thu, Aug 28, 2014 at 11:28 AM, Todd Weaver todd@m2n.com wrote:
It appears "If it is not supported by coreboot then you will have a lot of work in front of you."
This view, is based on not having the Intel code and writing your own
code
to set up the DRAM controllers. I imagine that it would be very
difficult
to write code for modern DRAM controllers, you have to read the EEPROMs on the DIMMs to determine the DRAM size and other characteristics, then set up the controller to match. Finally, DDR3 (used by this processor)
has a
training phase to get data accesses aligned in time. This might be
implemented
in hardware, or you might have to write code to do it. I don't know!
The truth here is that we NEED to have a blob-free version (libreboot),
so I have a lot of work ahead of me :)
The reality is that Intel has no plans to release code for Xeon E3-1200 v3 and HM86 Express. Coreboot's progress so far has been to integrate the blobs.
David