Hi Stefan,
Stefan Reinauer stefan.reinauer@coreboot.org writes:
On 4/17/11 6:07 AM, Sven Schnelle wrote:
Index: t60/Kconfig =================================================================== --- t60/Kconfig (revision 6509) +++ t60/Kconfig (working copy) @@ -56,4 +56,28 @@ int default 1 +config TI_PCMCIA_CARDBUS_CMDR + hex + default 0x0107 + +config TI_PCMCIA_CARDBUS_CLSR + hex + default 0x00 + +config TI_PCMCIA_CARDBUS_CLTR + hex + default 0x40 + +config TI_PCMCIA_CARDBUS_BCR + hex + default 0x07C0 + +config TI_PCMCIA_CARDBUS_SCR + hex + default 0x08449060 + +config TI_PCMCIA_CARDBUS_MRR + hex + default 0x00007522 + endifCan you please put these in a .c or .h file in the mainboard directory? I don't think we should add configuration variables for single registers in Kconfig.
Actually i've copied that from another Board using the pci1x2x cardbus controller, and was quite surprised that these settings are located in Kconfig. IMHO they should be configured in devicetree.cb via chip.h config. What do you think about this solution? Maybe we should do that in an extra patch, which moves those setting to chip config and converts all pci1x2x users?
Index: t60/dock.c =================================================================== --- t60/dock.c (revision 6509) +++ t60/dock.c (working copy) @@ -26,8 +26,9 @@ #include <delay.h> #include <arch/io.h> #include "dock.h" +#include "superio/nsc/pc87384/pc87384.h" +#include "ec/acpi/ec.h" #include "southbridge/intel/i82801gx/i82801gx.h" -#include "superio/nsc/pc87392/pc87392.h" static void dlpc_write_register(int reg, int value) { @@ -59,6 +60,7 @@ dlpc_write_register(0xf1, mode); } +drop new line?
Yes ;)
+ /* no GPIO events enabled for PORT0 */ + outb(0x00, 0x1622); + /* clear GPIO events on PORT0 */ + outb(0xff, 0x1623); + outb(0xff, 0x1624); + /* no GPIO events enabled for PORT1 */ + outb(0x00, 0x1626);Are you properly preventing the resource allocator from putting other resources on top of 0x16xx?
Yes, it's listed in devicetree.cb (which should prevent allocation). Debug log from boot:
PNP: 002e.7 60 <- [0x0000001620 - 0x000000162f] size 0x00000010 gran 0x04 io
+ outb(0x61, 0x15ec); + return inb(0x15ee) & 1; } +... and 0x15xx
same here, the 15e0 range is allocated in ec/lenovo/pmh7 (i'm not using the pmh7 function here because i don't want to have all the PMH7 code in SMM just for one register read)
Index: t60/mptable.c =================================================================== --- t60/mptable.c (revision 6509) +++ t60/mptable.c (working copy) @@ -62,9 +62,7 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) , 0x02, 0x17); /* LPC 0:1f.0 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x01, 0x02, 0x10); /* IDE 0:1f.1 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x02, 0x02, 0x10); /* SATA 0:1f.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x00, 0x02, 0x10); /* Cardbus 5:00.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x01, 0x02, 0x11); /* Firewire 5:00.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x02, 0x02, 0x12); /* SDHC 5:00.2 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x06, (0x00 << 2) | 0x00, 0x02, 0x10); /* Cardbus 5:00.0 */ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_HIGH, isa_bus, 0, MP_APIC_ALL, 0); smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_HIGH, isa_bus, 0, MP_APIC_ALL, 1);In general it would be better to look for the appropriate devices in the system, because someone might plug in a device with a bridge on the lower buses, effectively rendering your mptable useless.
MP table automation ftw!
Hmm, have to look how to do automatic generation of mptable. Thanks for the hint.
Sven.