Bit 7 of 48h is not set, to match Award, but I figured that this wouldn't make much difference anyway as this board is not using the FSB for interrupt delivery to the Local APIC.
No harm in flipping the bit to see what hapens though.
As far as I can tell the pin mux is all setup OK (58h[6] and also IOAPIC Rx3)
As what are coming through are illegal vectors, I am thinking that something is generating interrupts before a handler is in place or a completely unhandled exception is being generated.
If I change IOAPIC IRQ initialisation to have a vector in a legal range then the error changes
The one thing that I haven't managed to get done properly is disabling the special cpu frequency change. While it's a long shot it may be that this is causing something wierd to happen.
Think I'll have a closer read of the lapic spec too.
Jon
-----Original Message----- From: Rudolf Marek [mailto:r.marek@assembler.cz] Sent: 24 July 2009 21:40 To: Harrison, Jon (SELEX GALILEO, UK) Cc: coreboot@coreboot.org Subject: Re: [coreboot] IOAPIC Initialisation - How much do you have to do ??
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Harrison, Jon (SELEX GALILEO, UK) napsal(a):
Sooo. I've added MPtables and masked IRQ0 from boot but still get
APIC error on CPU0: 40(40)
Hi, seems like I'm bit online ;)
Check if bit 7 on 48h
7 APIC FSB Fixed at Low DW
It changes how the APIC is delivered. Also if external bus is used, you will need to check the pin multiplexer/multifunction is setup correctly.
Is there a kernel command line option that will turn on more verbose APIC output ?
Yes but not help apic=debug maybe
Rudolf
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