Author: ruik Date: 2008-12-05 00:42:36 +0100 (Fri, 05 Dec 2008) New Revision: 3796
Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c Log: This belongs to changeset 3795.
The patch changes the LDTSTOP length as well mostly default content of 0xec, 0xe4 and 0xe5 registers. I'm suspecting that the documentation may be wrong.
Furthermore this fix for powernow may not work on CPUs hit by errata #181. Workaround should be implemented. The powernow may not work on pre-A2 revisions of VT8237S silicon, revision reg is unknown.
Signed-off-by: Rudolf Marek r.marek@assembler.cz Acked-by: Peter Stuge peter@stuge.se
Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c 2008-12-04 23:37:12 UTC (rev 3795) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c 2008-12-04 23:42:36 UTC (rev 3796) @@ -92,6 +92,8 @@
#define K8_4RANK_DIMM_SUPPORT 1
+ + #include "northbridge/amd/amdk8/amdk8.h" #include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" @@ -102,6 +104,21 @@ #include "cpu/amd/car/copy_and_run.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" + +#define SB_VFSMAF 0 + +/* this function might fail on some K8 CPUs with errata #181 */ +static void ldtstop_sb(void) +{ + print_debug("toggle LDTSTP#\r\n"); + u8 reg = inb (VT8237R_ACPI_IO_BASE + 0x5c); + reg = reg ^ (1 << 0); + outb(reg, VT8237R_ACPI_IO_BASE + 0x5c); + reg = inb(VT8237R_ACPI_IO_BASE + 0x15); + print_debug("done\r\n"); +} + + #include "cpu/amd/model_fxx/fidvid.c" #include "northbridge/amd/amdk8/resourcemap.c"