Just FYI, here is what coreboot now says about devices:
<6>Phase 5: Done. <6>Show all devs... <8>root(Root Device): enabled 1 have_resources 0 initialized 0 <3>cpus: Unknown device path type: 0 <8>cpus(): enabled 1 have_resources 0 initialized 0 <8>apic_0(APIC: 00): enabled 1 have_resources 0 initialized 0 <8>domain_0_pci_1_0(PCI: 00:01.0): enabled 1 have_resources 0 initialized 0 <3>domain_0_pci0_18_0_pci_0_0_pci: Unknown device path type: 0 <8>domain_0_pci0_18_0_pci_0_0_pci(): enabled 1 have_resources 0 initialized 0 <8>domain_0_pci0_18_0_pci_0_0(PCI: 00:0a.0): enabled 1 have_resources 1 initialized 0 <8>domain_0_pci0_18_0_pci_4_0(PCI: 00:0e.0): enabled 0 have_resources 0 initialized 0 <8>domain_0_pci0_18_0(PCI: 00:18.0): enabled 1 have_resources 1 initialized 0 <8>domain_0_pci1_18_0(PCI: 00:18.0): enabled 1 have_resources 0 initialized 0 <8>domain_0_pci2_18_0_pci_2_0(PCI: 00:02.0): enabled 1 have_resources 0 initialized 0 <8>domain_0_pci2_18_0(PCI: 00:18.0): enabled 1 have_resources 0 initialized 0 <8>domain_0_pci_18_1(PCI: 00:18.1): enabled 1 have_resources 1 initialized 0 <8>domain_0_pci_18_2(PCI: 00:18.2): enabled 1 have_resources 1 initialized 0 <8>domain_0_pci_18_3(PCI: 00:18.3): enabled 1 have_resources 1 initialized 0 <8>domain_0_ioport_2e(IOPORT: 2e): enabled 1 have_resources 0 initialized 0 <8>domain_0(PCI_DOMAIN: 0000): enabled 1 have_resources 1 initialized 0 <8>dynamic PNP: 002e.0(PNP: 002e.0): enabled 1 have_resources 0 initialized 0 <8>dynamic PNP: 002e.1(PNP: 002e.1): enabled 1 have_resources 0 initialized 0 <8>dynamic PNP: 002e.2(PNP: 002e.2): enabled 1 have_resources 0 initialized 0 <8>dynamic PNP: 002e.3(PNP: 002e.3): enabled 1 have_resources 0 initialized 0 <8>dynamic PNP: 002e.5(PNP: 002e.5): enabled 1 have_resources 0 initialized 0 <8>dynamic PNP: 002e.6(PNP: 002e.6): enabled 1 have_resources 0 initialized 0 <8>dynamic PNP: 002e.7(PNP: 002e.7): enabled 1 have_resources 0 initialized 0 <8>dynamic PNP: 002e.8(PNP: 002e.8): enabled 1 have_resources 0 initialized 0 <8>dynamic PNP: 002e.9(PNP: 002e.9): enabled 1 have_resources 0 initialized 0 <8>dynamic PNP: 002e.a(PNP: 002e.a): enabled 1 have_resources 0 initialized 0 <8>dynamic PNP: 002e.b(PNP: 002e.b): enabled 1 have_resources 0 initialized 0 <8>dynamic PCI: 00:00.0(PCI: 00:06.0): enabled 1 have_resources 1 initialized 0 <8>dynamic PCI: 00:07.0(PCI: 00:07.0): enabled 1 have_resources 1 initialized 0 <8>dynamic PCI: 00:07.1(PCI: 00:07.1): enabled 1 have_resources 1 initialized 0 <8>dynamic PCI: 00:07.2(PCI: 00:07.2): enabled 1 have_resources 1 initialized 0 <8>dynamic PCI: 00:07.3(PCI: 00:07.3): enabled 1 have_resources 1 initialized 0 <8>dynamic PCI: 00:07.5(PCI: 00:07.5): enabled 1 have_resources 1 initialized 0 <8>dynamic PCI: 00:07.6(PCI: 00:07.6): enabled 1 have_resources 1 initialized 0 <8>dynamic PCI: 00:07.7(PCI: 00:07.7): enabled 1 have_resources 1 initialized 0 <8>dynamic PCI: 00:0a.1(PCI: 00:0a.1): enabled 1 have_resources 1 initialized 0 <8>dynamic PCI: 00:0b.0(PCI: 00:0b.0): enabled 1 have_resources 1 initialized 0 <8>dynamic PCI: 00:0b.1(PCI: 00:0b.1): enabled 1 have_resources 1 initialized 0 <8>dynamic PCI: 01:00.0(PCI: 01:00.0): enabled 1 have_resources 1 initialized 0 <8>dynamic PCI: 01:00.1(PCI: 01:00.1): enabled 1 have_resources 1 initialized 0 <8>dynamic PCI: 01:00.2(PCI: 01:00.2): enabled 1 have_resources 1 initialized 0 <8>dynamic PCI: 01:01.0(PCI: 01:01.0): enabled 1 have_resources 1 initialized 0 <8>dynamic PCI: 01:04.0(PCI: 01:04.0): enabled 1 have_resources 1 initialized 0 <8>dynamic PCI: 01:05.0(PCI: 01:05.0): enabled 1 have_resources 1 initialized 0
And here is the lockup: <6>Phase 6: Initializing devices... <7>Phase 6: Root Device init. <3>domain_0_pci0_18_0_pci_0_0_pci: Unknown device path type: 0 <7>Phase 6: init. <3>domain_0_pci0_18_0_pci_0_0_pci: Unknown device path type: 0 <0> missing resource: 10 <0> At this point it resets.
What I've realized is that 2 years ago we decided (in Hamburg) to get rid of the chip/device mess and unify around a device in both dts and C. It worked. I just forgot. Now we need to fix these last few nits and we are further along.
V3 is picking up speed. It's been a long, hard haul but we're getting there. Note that carl-daniels' naming scheme makes it quite easy to know what omain_0_pci0_18_0_pci_0_0_pci is ... ron