Author: rminnich Date: 2008-09-29 16:58:56 +0200 (Mon, 29 Sep 2008) New Revision: 872
Added: coreboot-v3/arch/x86/amd/model_fxx/stage1.c Modified: coreboot-v3/arch/x86/amd/model_fxx/dualcore.c coreboot-v3/arch/x86/amd/model_fxx/dualcore_id.c coreboot-v3/arch/x86/amd/model_fxx/fidvid.c coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c coreboot-v3/arch/x86/geodelx/stage1.c coreboot-v3/arch/x86/stage1.c coreboot-v3/arch/x86/stage1_mtrr.c coreboot-v3/include/arch/x86/amd/k8/k8.h coreboot-v3/include/arch/x86/cpu.h coreboot-v3/mainboard/amd/serengeti/Makefile coreboot-v3/mainboard/amd/serengeti/initram.c Log: Finally, after two years, put in real code for stop_ap(). Code has to be moved to stage1 ROM code. Make the struct for nodeid/coreid generic to x86. Create the functions for existing architectures are a model for future architectures (VIA coming soon we hope).
Move includes so that things build correctly now.
This is actually a small patch that impacted a number of files due to include order changes. This is build and boot tested on simnow and build tested on geode.
Signed-off-by: Ronald G. Minnich rminnich@gmail.com Acked-by: Stefan Reinauer stepan@coresystems.de
Modified: coreboot-v3/arch/x86/amd/model_fxx/dualcore.c =================================================================== --- coreboot-v3/arch/x86/amd/model_fxx/dualcore.c 2008-09-29 05:14:55 UTC (rev 871) +++ coreboot-v3/arch/x86/amd/model_fxx/dualcore.c 2008-09-29 14:58:56 UTC (rev 872) @@ -2,6 +2,7 @@ #include <mainboard.h> #include <types.h> #include <lib.h> +#include <cpu.h> #include <console.h> #include <globalvars.h> #include <device/device.h> @@ -9,7 +10,6 @@ #include <string.h> #include <msr.h> #include <io.h> -#include <cpu.h> #include <amd/k8/k8.h> #include <mc146818rtc.h> #include <spd.h>
Modified: coreboot-v3/arch/x86/amd/model_fxx/dualcore_id.c =================================================================== --- coreboot-v3/arch/x86/amd/model_fxx/dualcore_id.c 2008-09-29 05:14:55 UTC (rev 871) +++ coreboot-v3/arch/x86/amd/model_fxx/dualcore_id.c 2008-09-29 14:58:56 UTC (rev 872) @@ -2,6 +2,7 @@ #include <types.h> #include <lib.h> #include <console.h> +#include <cpu.h> #include <globalvars.h> #include <device/device.h> #include <device/pci.h>
Modified: coreboot-v3/arch/x86/amd/model_fxx/fidvid.c =================================================================== --- coreboot-v3/arch/x86/amd/model_fxx/fidvid.c 2008-09-29 05:14:55 UTC (rev 871) +++ coreboot-v3/arch/x86/amd/model_fxx/fidvid.c 2008-09-29 14:58:56 UTC (rev 872) @@ -1,6 +1,7 @@ #include <mainboard.h> #include <types.h> #include <lib.h> +#include <cpu.h> #include <console.h> #include <globalvars.h> #include <device/device.h> @@ -8,7 +9,6 @@ #include <string.h> #include <msr.h> #include <io.h> -#include <cpu.h> #include <amd/k8/k8.h> #include <mc146818rtc.h> #include <spd.h>
Modified: coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c =================================================================== --- coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c 2008-09-29 05:14:55 UTC (rev 871) +++ coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c 2008-09-29 14:58:56 UTC (rev 872) @@ -23,13 +23,13 @@ #include <types.h> #include <lib.h> #include <console.h> +#include <cpu.h> #include <globalvars.h> #include <device/device.h> #include <device/pci.h> #include <string.h> #include <msr.h> #include <io.h> -#include <cpu.h> #include <amd/k8/k8.h> #include <mc146818rtc.h> #include <spd.h> @@ -288,15 +288,6 @@ printk(BIOS_DEBUG, "\r\n"); }
-/** - * Stop all APs - * @param bsp_apicid The BSP apic id, to make sure we don't send ourselves the stop - */ -void allow_all_aps_stop(unsigned bsp_apicid) -{ - lapic_write(LAPIC_MSG_REG, (bsp_apicid << 24) | 0x44); // allow aps to stop -} - void STOP_CAR_AND_CPU(void) { disable_cache_as_ram(); // inline
Added: coreboot-v3/arch/x86/amd/model_fxx/stage1.c =================================================================== --- coreboot-v3/arch/x86/amd/model_fxx/stage1.c (rev 0) +++ coreboot-v3/arch/x86/amd/model_fxx/stage1.c 2008-09-29 14:58:56 UTC (rev 872) @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Advanced Micro Devices, Inc. + * Copyright (C) 2007 Stefan Reinauer + * Copyright (C) 2008 Ronald G. Minnich rminnich@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <mainboard.h> +#include <types.h> +#include <lib.h> +#include <console.h> +#include <cpu.h> +#include <globalvars.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <msr.h> +#include <io.h> +#include <amd/k8/k8.h> +#include <mc146818rtc.h> +#include <spd.h> +#include <lapic.h> + +/** + * Stop all APs + * @param bsp_apicid The BSP apic id, to make sure we don't send ourselves the stop + */ +void allow_all_aps_stop(unsigned bsp_apicid) +{ + lapic_write(LAPIC_MSG_REG, (bsp_apicid << 24) | 0x44); // allow aps to stop +} + +/** + * stop_ap. Called from stage1. + */ +void stop_ap(void) +{ + /* well, at time this is called, bsp_apicid *is* zero. It might change later. + * we need to figure this out. I don't know how. Global variable? + */ + allow_all_aps_stop(0); + post_code(POST_STAGE1_STOP_AP); +} +
Modified: coreboot-v3/arch/x86/geodelx/stage1.c =================================================================== --- coreboot-v3/arch/x86/geodelx/stage1.c 2008-09-29 05:14:55 UTC (rev 871) +++ coreboot-v3/arch/x86/geodelx/stage1.c 2008-09-29 14:58:56 UTC (rev 872) @@ -20,6 +20,7 @@
#include <types.h> #include <lib.h> +#include <cpu.h> #include <amd_geodelx.h> #include <console.h> #include <msr.h> @@ -48,6 +49,28 @@ }
/** + * Return core id/node id info. Always 0. + */ +struct node_core_id get_node_core_id(void) +{ + struct node_core_id id; + id.nodeid = 0; + id.coreid = 0; + return id; +} + +/** + * stop_ap. Hey, maybe someday we get multicore geodes. + * do not get upset about this code -- the cost is a one byte ret. + */ +void stop_ap(void) +{ + // nothing yet if ever + post_code(POST_STAGE1_STOP_AP); +} + + +/** * Disable Cache As RAM (CAR) after memory is setup. * * Geode can write back the cache contents to RAM and continue on.
Modified: coreboot-v3/arch/x86/stage1.c =================================================================== --- coreboot-v3/arch/x86/stage1.c 2008-09-29 05:14:55 UTC (rev 871) +++ coreboot-v3/arch/x86/stage1.c 2008-09-29 14:58:56 UTC (rev 872) @@ -21,6 +21,7 @@ #include <types.h> #include <io.h> #include <console.h> +#include <cpu.h> #include <globalvars.h> #include <lar.h> #include <string.h> @@ -44,12 +45,6 @@ void disable_car(void); void mainboard_pre_payload(void);
-static void stop_ap(void) -{ - // nothing yet - post_code(POST_STAGE1_STOP_AP); -} - static void enable_rom(void) { // nothing here yet @@ -165,6 +160,7 @@ int ret; struct mem_file archive; void *entry; + struct node_core_id me; #ifdef CONFIG_PAYLOAD_ELF_LOADER struct mem_file result; int elfboot_mem(struct lb_memory *mem, void *where, int size); @@ -183,16 +179,13 @@
post_code(POST_STAGE1_MAIN);
- // before we do anything, we want to stop if we dont run - // on the bootstrap processor. -#warning We do not want to check BIST here, we want to check whether we are BSC! - if (bist==0) { - // stop secondaries - stop_ap(); - } + /* before we do anything, we want to stop if we do not run + * on the bootstrap processor. + * stop_ap is responsible for NOT stopping the BSP + */ + stop_ap();
/* Initialize global variables before we can think of using them. - * NEVER run this on an AP! */ global_vars_init(&globvars); globvars.init_detected = init_detected;
Modified: coreboot-v3/arch/x86/stage1_mtrr.c =================================================================== --- coreboot-v3/arch/x86/stage1_mtrr.c 2008-09-29 05:14:55 UTC (rev 871) +++ coreboot-v3/arch/x86/stage1_mtrr.c 2008-09-29 14:58:56 UTC (rev 872) @@ -4,13 +4,13 @@ #include <types.h> #include <io.h> #include <console.h> +#include <cpu.h> #include <globalvars.h> #include <lar.h> #include <string.h> #include <tables.h> #include <lib.h> #include <mc146818rtc.h> -#include <cpu.h> #include <msr.h> #include <mtrr.h>
Modified: coreboot-v3/include/arch/x86/amd/k8/k8.h =================================================================== --- coreboot-v3/include/arch/x86/amd/k8/k8.h 2008-09-29 05:14:55 UTC (rev 871) +++ coreboot-v3/include/arch/x86/amd/k8/k8.h 2008-09-29 14:58:56 UTC (rev 872) @@ -639,16 +639,6 @@ /* dual core support */ unsigned int read_nb_cfg_54(void);
-struct node_core_id { - unsigned nodeid; - unsigned coreid; -}; - -/* use this to get the nodeid and core id of the current cpu - * (but not other CPUs) - */ -struct node_core_id get_node_core_id(void); - struct device; unsigned get_apicid_base(unsigned ioapic_num); void amd_sibling_init(struct device *cpu);
Modified: coreboot-v3/include/arch/x86/cpu.h =================================================================== --- coreboot-v3/include/arch/x86/cpu.h 2008-09-29 05:14:55 UTC (rev 871) +++ coreboot-v3/include/arch/x86/cpu.h 2008-09-29 14:58:56 UTC (rev 872) @@ -82,12 +82,28 @@ u8 x86_mask; };
+/* core and node id. This was special to k8 in v2 but is in fact quite generic */ +struct node_core_id { + unsigned nodeid; + unsigned coreid; +}; + +/* use this to get the nodeid and core id of the current cpu + * (but not other CPUs). We're going to make this supported on all CPUs. + * multicore is used everywhere now. For single socket/single core CPUs they can + * just return a struct with 0s. This will simplify the stage1 code. + */ +struct node_core_id get_node_core_id(void); + /* prototypes for functions that may or may not be compiled in depending on cpu type */ void set_var_mtrr_x( unsigned long reg, u32 base_lo, u32 base_hi, u32 size_lo, u32 size_hi, unsigned long type); void set_var_mtrr( unsigned long reg, unsigned long base, unsigned long size, unsigned long type);
+/* generic SMP functions required to be supported (even by non-SMP) + */ +void stop_ap(void);
/** * Generic CPUID function.
Modified: coreboot-v3/mainboard/amd/serengeti/Makefile =================================================================== --- coreboot-v3/mainboard/amd/serengeti/Makefile 2008-09-29 05:14:55 UTC (rev 871) +++ coreboot-v3/mainboard/amd/serengeti/Makefile 2008-09-29 14:58:56 UTC (rev 872) @@ -27,6 +27,8 @@ $(src)/southbridge/amd/amd8111/stage1_smbus.c \ $(src)/southbridge/amd/amd8111/stage1_ctrl.c \ $(src)/southbridge/amd/amd8111/stage1_enable_rom.c \ + $(src)/arch/x86/amd/model_fxx/dualcore_id.c \ + $(src)/arch/x86/amd/model_fxx/stage1.c \ $(src)/northbridge/amd/k8/coherent_ht.c \ $(src)/northbridge/amd/k8/libstage1.c \
@@ -38,10 +40,9 @@ $(src)/arch/x86/pci_ops_conf1.c \ $(src)/arch/x86/stage1_mtrr.c \ $(src)/southbridge/amd/amd8111/stage1_smbus.c \ - $(src)/arch/x86/amd/model_fxx/init_cpus.c \ $(src)/arch/x86/amd/model_fxx/dualcore.c \ - $(src)/arch/x86/amd/model_fxx/dualcore_id.c \ $(src)/arch/x86/amd/model_fxx/fidvid.c \ + $(src)/arch/x86/amd/model_fxx/init_cpus.c \ $(src)/lib/clog2.c
Modified: coreboot-v3/mainboard/amd/serengeti/initram.c =================================================================== --- coreboot-v3/mainboard/amd/serengeti/initram.c 2008-09-29 05:14:55 UTC (rev 871) +++ coreboot-v3/mainboard/amd/serengeti/initram.c 2008-09-29 14:58:56 UTC (rev 872) @@ -26,13 +26,13 @@ #include <types.h> #include <lib.h> #include <console.h> +#include <cpu.h> #include <globalvars.h> #include <device/device.h> #include <device/pci.h> #include <string.h> #include <msr.h> #include <io.h> -#include <cpu.h> #include <amd/k8/k8.h> #include <mc146818rtc.h> #include <spd.h>