Author: hailfinger Date: 2008-05-08 01:21:55 +0200 (Thu, 08 May 2008) New Revision: 677
Added: coreboot-v3/southbridge/amd/cs5536/ide Modified: coreboot-v3/mainboard/amd/db800/dts coreboot-v3/mainboard/amd/norwich/dts coreboot-v3/mainboard/artecgroup/dbe61/dts coreboot-v3/mainboard/artecgroup/dbe62/dts coreboot-v3/mainboard/pcengines/alix1c/dts coreboot-v3/mainboard/pcengines/alix2c3/dts coreboot-v3/southbridge/amd/cs5536/cs5536.c coreboot-v3/southbridge/amd/cs5536/dts Log: Move CS5536 IDE configuration into a separate dts and its own PCI device.
Fix dbe62 IDE/NAND selection.
Build-tested on db800, norwich, dbe62, alix.1c, alix.2c3. No additional breakage for dbe61.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net Acked-by: Ronald G. Minnich rminnich@gmail.com Acked-by: Stefan Reinauer stepan@coresystems.de
Modified: coreboot-v3/mainboard/amd/db800/dts =================================================================== --- coreboot-v3/mainboard/amd/db800/dts 2008-05-05 13:59:01 UTC (rev 676) +++ coreboot-v3/mainboard/amd/db800/dts 2008-05-07 23:21:55 UTC (rev 677) @@ -34,7 +34,6 @@ }; pci@15,0 { /config/("southbridge/amd/cs5536/dts"); - enable_ide = "1"; /* Interrupt enables for LPC bus. * Each bit is an IRQ 0-15. */ lpc_serirq_enable = "0x000010da"; @@ -47,6 +46,10 @@ enable_gpio_int_route = "0x0D0C0700"; enable_USBP4_device = "1"; }; + pci@15,2 { + /config/("southbridge/amd/cs5536/ide"); + enable_ide = "1"; + }; ioport@46 { /config/("superio/winbond/w83627hf/dts"); com1enable = "1";
Modified: coreboot-v3/mainboard/amd/norwich/dts =================================================================== --- coreboot-v3/mainboard/amd/norwich/dts 2008-05-05 13:59:01 UTC (rev 676) +++ coreboot-v3/mainboard/amd/norwich/dts 2008-05-07 23:21:55 UTC (rev 677) @@ -34,7 +34,6 @@ }; pci@15,0 { /config/("southbridge/amd/cs5536/dts"); - enable_ide = "1"; /* Interrupt enables for LPC bus. * Each bit is an IRQ 0-15. */ lpc_serirq_enable = "0x00001002"; @@ -50,5 +49,9 @@ com1_address = "0x3f8"; com1_irq = "4"; }; + pci@15,2 { + /config/("southbridge/amd/cs5536/ide"); + enable_ide = "1"; + }; }; };
Modified: coreboot-v3/mainboard/artecgroup/dbe61/dts =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe61/dts 2008-05-05 13:59:01 UTC (rev 676) +++ coreboot-v3/mainboard/artecgroup/dbe61/dts 2008-05-07 23:21:55 UTC (rev 677) @@ -105,5 +105,8 @@ com2_address = "0x3f8"; com2_irq = "4"; }; + pci@15,2 { + /config/("southbridge/amd/cs5536/ide"); + }; }; };
Modified: coreboot-v3/mainboard/artecgroup/dbe62/dts =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe62/dts 2008-05-05 13:59:01 UTC (rev 676) +++ coreboot-v3/mainboard/artecgroup/dbe62/dts 2008-05-07 23:21:55 UTC (rev 677) @@ -34,7 +34,6 @@ }; pci@15,0 { /config/("southbridge/amd/cs5536/dts"); - enable_ide = "1"; /* Interrupt enables for LPC bus. * Each bit is an IRQ 0-15. */ lpc_serirq_enable = "0x00001002"; @@ -54,5 +53,8 @@ /* Set com2 IRQ to be what is usually COM1 */ com2_irq = "4"; }; + pci@15,2 { + /config/("southbridge/amd/cs5536/ide"); + }; }; };
Modified: coreboot-v3/mainboard/pcengines/alix1c/dts =================================================================== --- coreboot-v3/mainboard/pcengines/alix1c/dts 2008-05-05 13:59:01 UTC (rev 676) +++ coreboot-v3/mainboard/pcengines/alix1c/dts 2008-05-07 23:21:55 UTC (rev 677) @@ -34,7 +34,6 @@ }; pci@15,0 { /config/("southbridge/amd/cs5536/dts"); - enable_ide = "1"; /* Interrupt enables for LPC bus. * Each bit is an IRQ 0-15. */ lpc_serirq_enable = "0x000010da"; @@ -46,6 +45,10 @@ * See virtual PIC spec. */ enable_gpio_int_route = "0x0D0C0700"; }; + pci@15,2 { + /config/("southbridge/amd/cs5536/ide"); + enable_ide = "1"; + }; ioport@46 { /config/("superio/winbond/w83627hf/dts"); com1enable = "1";
Modified: coreboot-v3/mainboard/pcengines/alix2c3/dts =================================================================== --- coreboot-v3/mainboard/pcengines/alix2c3/dts 2008-05-05 13:59:01 UTC (rev 676) +++ coreboot-v3/mainboard/pcengines/alix2c3/dts 2008-05-07 23:21:55 UTC (rev 677) @@ -32,7 +32,6 @@ }; pci@15,0 { /config/("southbridge/amd/cs5536/dts"); - enable_ide = "1"; /* Interrupt enables for LPC bus. * Each bit is an IRQ 0-15. */ lpc_serirq_enable = "0x000010da"; @@ -50,5 +49,9 @@ /* this board does not really have vga; disable it (pci device 00:01.1) */ unwanted_vpci = < 80000900 0 >; }; + pci@15,2 { + /config/("southbridge/amd/cs5536/ide"); + enable_ide = "1"; + }; }; };
Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.c =================================================================== --- coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-05-05 13:59:01 UTC (rev 676) +++ coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-05-07 23:21:55 UTC (rev 677) @@ -590,6 +590,11 @@ { u32 ide_cfg;
+ struct southbridge_amd_cs5536_ide_config *ide = + (struct southbridge_amd_cs5536_ide_config *)dev->device_configuration; + if (!ide->enable_ide) + return; + printk(BIOS_DEBUG, "cs5536_ide: %s\n", __func__); /* GPIO and IRQ setup are handled in the main chipset code. */
@@ -654,9 +659,6 @@ hide_vpci(sb->unwanted_vpci[i]); }
- if (sb->enable_ide) - ide_init(dev); - cs5536_setup_power_button(sb);
printk(BIOS_SPEW, "cs5536: %s() Exit\n", __FUNCTION__); @@ -688,3 +690,17 @@ .phase6_init = southbridge_init, };
+struct device_operations cs5536_ide = { + .id = {.type = DEVICE_ID_PCI, + .u = {.pci = {.vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_CS5536_B0_IDE}}}, + .constructor = default_device_constructor, +#warning FIXME: what has to go in phase3_scan? + .phase3_scan = 0, + .phase4_read_resources = pci_dev_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = pci_dev_enable_resources, + .phase6_init = ide_init, + .ops_pci = &pci_dev_ops_pci, +}; +
Modified: coreboot-v3/southbridge/amd/cs5536/dts =================================================================== --- coreboot-v3/southbridge/amd/cs5536/dts 2008-05-05 13:59:01 UTC (rev 676) +++ coreboot-v3/southbridge/amd/cs5536/dts 2008-05-07 23:21:55 UTC (rev 677) @@ -36,9 +36,6 @@ /* 0:IDE 1:FLASH, if you are using NAND flash instead of IDE drive. */ enable_ide_nand_flash = "0";
- /* IDE: enable CS5536 IDE. There may be a different IDE controller on board */ - enable_ide = "0"; - /* Enable USB Port 4 (0:host 1:device). */ enable_USBP4_device = "0";
Added: coreboot-v3/southbridge/amd/cs5536/ide =================================================================== --- coreboot-v3/southbridge/amd/cs5536/ide (rev 0) +++ coreboot-v3/southbridge/amd/cs5536/ide 2008-05-07 23:21:55 UTC (rev 677) @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Ronald G. Minnich rminnich@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +{ + device_operations = "cs5536_ide"; + + /* IDE: enable CS5536 IDE. There may be a different IDE controller on board */ + enable_ide = "0"; +};