Author: mraudsepp Date: 2009-01-09 19:12:05 +0100 (Fri, 09 Jan 2009) New Revision: 1113
Added: coreboot-v3/southbridge/amd/cs5536/nand Modified: coreboot-v3/mainboard/artecgroup/dbe61/dts coreboot-v3/mainboard/artecgroup/dbe62/dts coreboot-v3/southbridge/amd/cs5536/cs5536.c Log: cs5536: Add a NAND device and do the IDE PCI header disabling on time.
This implements a nand device, akin to the ide device to follow the coreboot-v3 device tree design better. It allows us to do the IDE PCI header early enough in a clean way - the hide_vpci was called way too late before - in phase6 of southbridge device, but we need the Flash header active instead of IDE in the VSA2 before bus scans happen, or the PCI device gets disabled in coreboot understanding by the time we get it enabled in VSA2. It makes NAND setup work better, but still not completely. There is a VSA2 bug for which I made a patch, but waiting on a new binary to test if after that everything works or not. A quick hack to workaround the VSA2 bug suggests something further will still need fixing. There are also more potential opportunities to shuffle NAND code around to match v3 approach better, but that's a next step for me after NAND setup actually works right in the current form.
Also corrected the documentation of ide_init() to match current reality.
Signed-off-by: Mart Raudsepp mart.raudsepp@artecdesign.ee Acked-by: Peter Stuge peter@stuge.se
Modified: coreboot-v3/mainboard/artecgroup/dbe61/dts =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe61/dts 2009-01-09 14:17:06 UTC (rev 1112) +++ coreboot-v3/mainboard/artecgroup/dbe61/dts 2009-01-09 18:12:05 UTC (rev 1113) @@ -109,6 +109,9 @@ /* USB Port Power Handling setting. */ pph = "0xf5"; }; + pci@f,1 { + /config/("southbridge/amd/cs5536/nand"); + }; pci@f,2 { /config/("southbridge/amd/cs5536/ide"); };
Modified: coreboot-v3/mainboard/artecgroup/dbe62/dts =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe62/dts 2009-01-09 14:17:06 UTC (rev 1112) +++ coreboot-v3/mainboard/artecgroup/dbe62/dts 2009-01-09 18:12:05 UTC (rev 1113) @@ -63,6 +63,9 @@ /* USB Port Power Handling setting. */ pph = "0xf5"; }; + pci@f,1 { + /config/("southbridge/amd/cs5536/nand"); + }; pci@f,2 { /config/("southbridge/amd/cs5536/ide"); };
Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.c =================================================================== --- coreboot-v3/southbridge/amd/cs5536/cs5536.c 2009-01-09 14:17:06 UTC (rev 1112) +++ coreboot-v3/southbridge/amd/cs5536/cs5536.c 2009-01-09 18:12:05 UTC (rev 1113) @@ -98,6 +98,23 @@ }
/** + * Enables the FLASH PCI header when NAND device existing in mainboard device + * tree. Used when the mainboard has a FLASH part instead of an IDE drive and + * that fact is expressed in the mainboard device tree. + * Must be called after VSA init but before PCI scans to enable the flash + * PCI device header early enough - that is .phase2_fixup of the device. + * + * @param dev The device. + */ +static void nand_phase2(struct device *dev) +{ + if (dev->enabled) { + /* Tell VSA to use FLASH PCI header. Not IDE header. */ + hide_vpci(0x800079C4); + } +} + +/** * Power button setup. * * Setup GPIO24, it is the external signal for CS5536 vsb_work_aux which @@ -170,16 +187,6 @@ printk(BIOS_DEBUG, "chipset_flash_setup: Finish\n"); }
-/** - * Use this in the event that you have a FLASH part instead of an IDE drive. - * Run after VSA init to enable the flash PCI device header. - */ -static void enable_ide_nand_flash_header(void) -{ - /* Tell VSA to use FLASH PCI header. Not IDE header. */ - hide_vpci(0x800079C4); -} - #define RTC_CENTURY 0x32 #define RTC_DOMA 0x3D #define RTC_MONA 0x3E @@ -601,8 +608,8 @@ #define IDE_ETC 0x50
/** - * Enabled the IDE. This is code that is optionally run if the ide_enable is set - * in the mainboard dts. + * Enables the IDE. This is code that is run if there is an ide device in the mainboard + * device tree and it has set non-zero "enable_ide". * * @param dev The device */ @@ -658,11 +665,6 @@ printk(BIOS_SPEW, "cs5536: done second call vr_write\n"); }
- printk(BIOS_ERR, "cs5536: %s: enable_ide_nand_flash is %d\n", - __FUNCTION__, sb->enable_ide_nand_flash); - if (sb->enable_ide_nand_flash != 0) - enable_ide_nand_flash_header(); - enable_USB_port4(sb);
/* disable unwanted virtual PCI devices */ @@ -733,3 +735,16 @@ .ops_pci = &pci_dev_ops_pci, };
+struct device_operations cs5536_nand = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_CS5536_FLASH}}}, + .constructor = default_device_constructor, + .phase2_fixup = nand_phase2, + .phase3_scan = 0, + .phase4_read_resources = pci_dev_read_resources, + .phase4_set_resources = pci_set_resources, + .phase5_enable_resources = pci_dev_enable_resources, + .phase6_init = 0, /* No Option ROMs */ + .ops_pci = &pci_dev_ops_pci, +};
Added: coreboot-v3/southbridge/amd/cs5536/nand =================================================================== --- coreboot-v3/southbridge/amd/cs5536/nand (rev 0) +++ coreboot-v3/southbridge/amd/cs5536/nand 2009-01-09 18:12:05 UTC (rev 1113) @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Mart Raudsepp mart.raudsepp@artecdesign.ee + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +{ + device_operations = "cs5536_nand"; +};