Author: stepan Date: Tue Apr 20 15:22:02 2010 New Revision: 5460 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5460
Log: - move src/arch/i386/smp/ioapic.c to src/arch/i386/lib/ioapic.c (has nothing to do with SMP) - move src/arch/i386/smp/mpspec.c to src/arch/i386/boot/mpspec.c (where acpi, pirq and coreboot table generation lives) - modify src/arch/i386/boot/Makefile.inc, src/arch/i386/lib/Makefile.inc and src/arch/i386/smp/Makefile.inc accordingly - src/arch/i386/smp is now empty. drop it. - drop src/arch/i386/init/car.S (unused)
Signed-off-by: Stefan Reinauer stepan@coresystems.de Acked-by: Patrick Georgi patrick.georgi@coresystems.de
Added: trunk/src/arch/i386/boot/mpspec.c - copied unchanged from r5458, trunk/src/arch/i386/smp/mpspec.c trunk/src/arch/i386/lib/ioapic.c - copied unchanged from r5458, trunk/src/arch/i386/smp/ioapic.c Deleted: trunk/src/arch/i386/init/car.S trunk/src/arch/i386/smp/ Modified: trunk/src/arch/i386/boot/Makefile.inc trunk/src/arch/i386/lib/Makefile.inc
Modified: trunk/src/arch/i386/boot/Makefile.inc ============================================================================== --- trunk/src/arch/i386/boot/Makefile.inc Tue Apr 20 13:03:41 2010 (r5459) +++ trunk/src/arch/i386/boot/Makefile.inc Tue Apr 20 15:22:02 2010 (r5460) @@ -3,6 +3,7 @@ obj-$(CONFIG_MULTIBOOT) += multiboot.o obj-y += gdt.o obj-y += tables.o +obj-$(CONFIG_GENERATE_MP_TABLE) += mpspec.o obj-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.o obj-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.o obj-$(CONFIG_GENERATE_ACPI_TABLES) += acpigen.o
Copied: trunk/src/arch/i386/boot/mpspec.c (from r5458, trunk/src/arch/i386/smp/mpspec.c) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/arch/i386/boot/mpspec.c Tue Apr 20 15:22:02 2010 (r5460, copy of r5458, trunk/src/arch/i386/smp/mpspec.c) @@ -0,0 +1,306 @@ +#include <console/console.h> +#include <device/path.h> +#include <device/pci_ids.h> +#include <cpu/cpu.h> +#include <arch/smp/mpspec.h> +#include <string.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> + +unsigned char smp_compute_checksum(void *v, int len) +{ + unsigned char *bytes; + unsigned char checksum; + int i; + bytes = v; + checksum = 0; + for(i = 0; i < len; i++) { + checksum -= bytes[i]; + } + return checksum; +} + +void *smp_write_floating_table(unsigned long addr) +{ + /* 16 byte align the table address */ + addr = (addr + 0xf) & (~0xf); + return smp_write_floating_table_physaddr(addr, addr + SMP_FLOATING_TABLE_LEN); +} + +void *smp_write_floating_table_physaddr(unsigned long addr, unsigned long mpf_physptr) +{ + struct intel_mp_floating *mf; + void *v; + + v = (void *)addr; + mf = v; + mf->mpf_signature[0] = '_'; + mf->mpf_signature[1] = 'M'; + mf->mpf_signature[2] = 'P'; + mf->mpf_signature[3] = '_'; + mf->mpf_physptr = mpf_physptr; + mf->mpf_length = 1; + mf->mpf_specification = 4; + mf->mpf_checksum = 0; + mf->mpf_feature1 = 0; + mf->mpf_feature2 = 0; + mf->mpf_feature3 = 0; + mf->mpf_feature4 = 0; + mf->mpf_feature5 = 0; + mf->mpf_checksum = smp_compute_checksum(mf, mf->mpf_length*16); + return v; +} + +void *smp_next_mpc_entry(struct mp_config_table *mc) +{ + void *v; + v = (void *)(((char *)mc) + mc->mpc_length); + return v; +} +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) +{ + mc->mpc_length += length; + mc->mpc_entry_count++; +} + +void *smp_next_mpe_entry(struct mp_config_table *mc) +{ + void *v; + v = (void *)(((char *)mc) + mc->mpc_length + mc->mpe_length); + return v; +} +static void smp_add_mpe_entry(struct mp_config_table *mc, mpe_t mpe) +{ + mc->mpe_length += mpe->mpe_length; +} + +void smp_write_processor(struct mp_config_table *mc, + unsigned char apicid, unsigned char apicver, + unsigned char cpuflag, unsigned int cpufeature, + unsigned int featureflag) +{ + struct mpc_config_processor *mpc; + mpc = smp_next_mpc_entry(mc); + memset(mpc, '\0', sizeof(*mpc)); + mpc->mpc_type = MP_PROCESSOR; + mpc->mpc_apicid = apicid; + mpc->mpc_apicver = apicver; + mpc->mpc_cpuflag = cpuflag; + mpc->mpc_cpufeature = cpufeature; + mpc->mpc_featureflag = featureflag; + smp_add_mpc_entry(mc, sizeof(*mpc)); +} + +/* If we assume a symmetric processor configuration we can + * get all of the information we need to write the processor + * entry from the bootstrap processor. + * Plus I don't think linux really even cares. + * Having the proper apicid's in the table so the non-bootstrap + * processors can be woken up should be enough. + */ +void smp_write_processors(struct mp_config_table *mc) +{ + int boot_apic_id; + unsigned apic_version; + unsigned cpu_features; + unsigned cpu_feature_flags; + struct cpuid_result result; + device_t cpu; + + boot_apic_id = lapicid(); + apic_version = lapic_read(LAPIC_LVR) & 0xff; + result = cpuid(1); + cpu_features = result.eax; + cpu_feature_flags = result.edx; + for(cpu = all_devices; cpu; cpu = cpu->next) { + unsigned long cpu_flag; + if ((cpu->path.type != DEVICE_PATH_APIC) || + (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) + { + continue; + } + if (!cpu->enabled) { + continue; + } + cpu_flag = MPC_CPU_ENABLED; + if (boot_apic_id == cpu->path.apic.apic_id) { + cpu_flag = MPC_CPU_ENABLED | MPC_CPU_BOOTPROCESSOR; + } + smp_write_processor(mc, + cpu->path.apic.apic_id, apic_version, + cpu_flag, cpu_features, cpu_feature_flags + ); + } +} + +void smp_write_bus(struct mp_config_table *mc, + unsigned char id, const char *bustype) +{ + struct mpc_config_bus *mpc; + mpc = smp_next_mpc_entry(mc); + memset(mpc, '\0', sizeof(*mpc)); + mpc->mpc_type = MP_BUS; + mpc->mpc_busid = id; + memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); + smp_add_mpc_entry(mc, sizeof(*mpc)); +} + +void smp_write_ioapic(struct mp_config_table *mc, + unsigned char id, unsigned char ver, + unsigned long apicaddr) +{ + struct mpc_config_ioapic *mpc; + mpc = smp_next_mpc_entry(mc); + memset(mpc, '\0', sizeof(*mpc)); + mpc->mpc_type = MP_IOAPIC; + mpc->mpc_apicid = id; + mpc->mpc_apicver = ver; + mpc->mpc_flags = MPC_APIC_USABLE; + mpc->mpc_apicaddr = apicaddr; + smp_add_mpc_entry(mc, sizeof(*mpc)); +} + +void smp_write_intsrc(struct mp_config_table *mc, + unsigned char irqtype, unsigned short irqflag, + unsigned char srcbus, unsigned char srcbusirq, + unsigned char dstapic, unsigned char dstirq) +{ + struct mpc_config_intsrc *mpc; + mpc = smp_next_mpc_entry(mc); + memset(mpc, '\0', sizeof(*mpc)); + mpc->mpc_type = MP_INTSRC; + mpc->mpc_irqtype = irqtype; + mpc->mpc_irqflag = irqflag; + mpc->mpc_srcbus = srcbus; + mpc->mpc_srcbusirq = srcbusirq; + mpc->mpc_dstapic = dstapic; + mpc->mpc_dstirq = dstirq; + smp_add_mpc_entry(mc, sizeof(*mpc)); +#ifdef DEBUG_MPTABLE + printk(BIOS_DEBUG, "add intsrc srcbus 0x%x srcbusirq 0x%x, dstapic 0x%x, dstirq 0x%x\n", + srcbus, srcbusirq, dstapic, dstirq); + hexdump(__func__, mpc, sizeof(*mpc)); +#endif +} + +void smp_write_intsrc_pci_bridge(struct mp_config_table *mc, + unsigned char irqtype, unsigned short irqflag, + struct device *dev, + unsigned char dstapic, unsigned char *dstirq) +{ + struct device *child; + + int linkn; + int i; + int srcbus; + int slot; + + struct bus *link; + unsigned char dstirq_x[4]; + + for (linkn = 0; linkn < dev->links; linkn++) { + + link = &dev->link[linkn]; + child = link->children; + srcbus = link->secondary; + + while (child) { + if (child->path.type != DEVICE_PATH_PCI) + goto next; + + slot = (child->path.pci.devfn >> 3); + /* round pins */ + for (i = 0; i < 4; i++) + dstirq_x[i] = dstirq[(i + slot) % 4]; + + if ((child->class >> 16) != PCI_BASE_CLASS_BRIDGE) { + /* pci device */ + printk(BIOS_DEBUG, "route irq: %s\n", dev_path(child)); + for (i = 0; i < 4; i++) + smp_write_intsrc(mc, irqtype, irqflag, srcbus, (slot<<2)|i, dstapic, dstirq_x[i]); + goto next; + } + + switch (child->class>>8) { + case PCI_CLASS_BRIDGE_PCI: + case PCI_CLASS_BRIDGE_PCMCIA: + case PCI_CLASS_BRIDGE_CARDBUS: + printk(BIOS_DEBUG, "route irq bridge: %s\n", dev_path(child)); + smp_write_intsrc_pci_bridge(mc, irqtype, irqflag, child, dstapic, dstirq_x); + } + + next: + child = child->sibling; + } + + } +} + +void smp_write_lintsrc(struct mp_config_table *mc, + unsigned char irqtype, unsigned short irqflag, + unsigned char srcbusid, unsigned char srcbusirq, + unsigned char destapic, unsigned char destapiclint) +{ + struct mpc_config_lintsrc *mpc; + mpc = smp_next_mpc_entry(mc); + memset(mpc, '\0', sizeof(*mpc)); + mpc->mpc_type = MP_LINTSRC; + mpc->mpc_irqtype = irqtype; + mpc->mpc_irqflag = irqflag; + mpc->mpc_srcbusid = srcbusid; + mpc->mpc_srcbusirq = srcbusirq; + mpc->mpc_destapic = destapic; + mpc->mpc_destapiclint = destapiclint; + smp_add_mpc_entry(mc, sizeof(*mpc)); +} + +void smp_write_address_space(struct mp_config_table *mc, + unsigned char busid, unsigned char address_type, + unsigned int address_base_low, unsigned int address_base_high, + unsigned int address_length_low, unsigned int address_length_high) +{ + struct mp_exten_system_address_space *mpe; + mpe = smp_next_mpe_entry(mc); + memset(mpe, '\0', sizeof(*mpe)); + mpe->mpe_type = MPE_SYSTEM_ADDRESS_SPACE; + mpe->mpe_length = sizeof(*mpe); + mpe->mpe_busid = busid; + mpe->mpe_address_type = address_type; + mpe->mpe_address_base_low = address_base_low; + mpe->mpe_address_base_high = address_base_high; + mpe->mpe_address_length_low = address_length_low; + mpe->mpe_address_length_high = address_length_high; + smp_add_mpe_entry(mc, (mpe_t)mpe); +} + + +void smp_write_bus_hierarchy(struct mp_config_table *mc, + unsigned char busid, unsigned char bus_info, + unsigned char parent_busid) +{ + struct mp_exten_bus_hierarchy *mpe; + mpe = smp_next_mpe_entry(mc); + memset(mpe, '\0', sizeof(*mpe)); + mpe->mpe_type = MPE_BUS_HIERARCHY; + mpe->mpe_length = sizeof(*mpe); + mpe->mpe_busid = busid; + mpe->mpe_bus_info = bus_info; + mpe->mpe_parent_busid = parent_busid; + smp_add_mpe_entry(mc, (mpe_t)mpe); +} + +void smp_write_compatibility_address_space(struct mp_config_table *mc, + unsigned char busid, unsigned char address_modifier, + unsigned int range_list) +{ + struct mp_exten_compatibility_address_space *mpe; + mpe = smp_next_mpe_entry(mc); + memset(mpe, '\0', sizeof(*mpe)); + mpe->mpe_type = MPE_COMPATIBILITY_ADDRESS_SPACE; + mpe->mpe_length = sizeof(*mpe); + mpe->mpe_busid = busid; + mpe->mpe_address_modifier = address_modifier; + mpe->mpe_range_list = range_list; + smp_add_mpe_entry(mc, (mpe_t)mpe); +} +
Modified: trunk/src/arch/i386/lib/Makefile.inc ============================================================================== --- trunk/src/arch/i386/lib/Makefile.inc Tue Apr 20 13:03:41 2010 (r5459) +++ trunk/src/arch/i386/lib/Makefile.inc Tue Apr 20 15:22:02 2010 (r5460) @@ -5,6 +5,7 @@ obj-y += pci_ops_mmconf.o obj-y += pci_ops_auto.o obj-y += exception.o +obj-$(CONFIG_IOAPIC) += ioapic.o
initobj-y += printk_init.o initobj-y += cbfs_and_run.o
Copied: trunk/src/arch/i386/lib/ioapic.c (from r5458, trunk/src/arch/i386/smp/ioapic.c) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/arch/i386/lib/ioapic.c Tue Apr 20 15:22:02 2010 (r5460, copy of r5458, trunk/src/arch/i386/smp/ioapic.c) @@ -0,0 +1,135 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <arch/ioapic.h> +#include <console/console.h> +#include <cpu/x86/lapic.h> + +static u32 io_apic_read(u32 ioapic_base, u32 reg) +{ + write32(ioapic_base, reg); + return read32(ioapic_base + 0x10); +} + +static void io_apic_write(u32 ioapic_base, u32 reg, u32 value) +{ + write32(ioapic_base, reg); + write32(ioapic_base + 0x10, value); +} + + +void clear_ioapic(u32 ioapic_base) +{ + u32 low, high; + u32 i, ioapic_interrupts; + + printk(BIOS_DEBUG, "IOAPIC: Clearing IOAPIC at 0x%08x\n", ioapic_base); + + /* Read the available number of interrupts */ + ioapic_interrupts = (io_apic_read(ioapic_base, 1) >> 16) & 0xff; + if (!ioapic_interrupts || ioapic_interrupts == 0xff) + ioapic_interrupts = 24; + printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts); + + low = DISABLED; + high = NONE; + + for (i = 0; i < ioapic_interrupts; i++) { + io_apic_write(ioapic_base, i * 2 + 0x10, low); + io_apic_write(ioapic_base, i * 2 + 0x11, high); + + printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", i, high, low); + } + + if (io_apic_read(ioapic_base, 0x10) == 0xffffffff) { + printk(BIOS_WARNING, "IO APIC not responding.\n"); + return; + } +} + +void setup_ioapic(u32 ioapic_base, u8 ioapic_id) +{ + u32 bsp_lapicid = lapicid(); + u32 low, high; + u32 i, ioapic_interrupts; + + printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n", ioapic_base); + printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = %02x\n", + bsp_lapicid); + + if (ioapic_id) { + printk(BIOS_DEBUG, "IOAPIC: ID = 0x%02x\n", ioapic_id); + /* Set IOAPIC ID if it has been specified */ + io_apic_write(ioapic_base, 0x00, + (io_apic_read(ioapic_base, 0x00) & 0xfff0ffff) | + (ioapic_id << 24)); + } + + /* Read the available number of interrupts */ + ioapic_interrupts = (io_apic_read(ioapic_base, 1) >> 16) & 0xff; + if (!ioapic_interrupts || ioapic_interrupts == 0xff) + ioapic_interrupts = 24; + printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts); + + +// XXX this decision should probably be made elsewhere, and +// it's the C3, not the EPIA this depends on. +#if defined(CONFIG_EPIA_VT8237R_INIT) && CONFIG_EPIA_VT8237R_INIT +#define IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS +#else +#define IOAPIC_INTERRUPTS_ON_FSB +#endif + +#ifdef IOAPIC_INTERRUPTS_ON_FSB + /* For the Pentium 4 and above APICs deliver their interrupts + * on the front side bus, enable that. + */ + printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n"); + io_apic_write(ioapic_base, 0x03, io_apic_read(ioapic_base, 0x03) | (1 << 0)); +#endif +#ifdef IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS + printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n"); + io_apic_write(ioapic_base, 0x03, 0); +#endif + + /* Enable Virtual Wire Mode */ + low = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT; + high = bsp_lapicid << (56 - 32); + + io_apic_write(ioapic_base, 0x10, low); + io_apic_write(ioapic_base, 0x11, high); + + if (io_apic_read(ioapic_base, 0x10) == 0xffffffff) { + printk(BIOS_WARNING, "IO APIC not responding.\n"); + return; + } + + printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", 0, high, low); + + low = DISABLED; + high = NONE; + + for (i = 1; i < ioapic_interrupts; i++) { + io_apic_write(ioapic_base, i * 2 + 0x10, low); + io_apic_write(ioapic_base, i * 2 + 0x11, high); + + printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", i, high, low); + } +}