[coreboot] [PATCH] flashrom: nic3com: add 16bit and 32bit chip reads/writes

[Carl-Daniel Hailfinger]

Add 16 bit and 32 bit chip reads/writes to the nic3com driver. It
emulates those accesses by splitting them to 8 bit accesses.

Signed-off-by: Carl-Daniel Hailfinger

Index: flashrom-nic3com_16bit_32bit_read_write/nic3com.c
===================================================================
--- flashrom-nic3com_16bit_32bit_read_write/nic3com.c	(Revision 516)
+++ flashrom-nic3com_16bit_32bit_read_write/nic3com.c	(Arbeitskopie)
@@ -93,12 +93,18 @@
    OUTB(val, io_base_addr + BIOS_ROM_DATA);
 }

+/* Little-endian */
 void nic3com_chip_writew(uint16_t val, volatile void *addr)
 {
+	chip_writeb(val & 0xff, addr);
+	chip_writeb((val >> 8) & 0xff, addr + 1);
 }

+/* Little-endian */
 void nic3com_chip_writel(uint32_t val, volatile void *addr)
 {
+	chip_writew(val & 0xffff, addr);
+	chip_writew((val >> 16) & 0xffff, addr + 2);
 }

uint8_t nic3com_chip_readb(const volatile void *addr)
@@ -111,12 +117,20 @@
    return val;
 }

+/* Little-endian */
 uint16_t nic3com_chip_readw(const volatile void *addr)
 {
-	return 0xffff;
+	uint16_t val;
+	val = chip_readb(addr);
+	val |= chip_readb(addr + 1) << 8;
+	return val;
 }

+/* Little-endian */
 uint32_t nic3com_chip_readl(const volatile void *addr)
 {
-	return 0xffffffff;
+	uint32_t val;
+	val = chip_readw(addr);
+	val |= chip_readw(addr + 2) << 16;
+	return val;
 }