Hello,
I have successfully used the cache in the K8 processor as RAM on the AMD Serenade mainboard. The cache as ram is used as a tiny stack space for the code generated by GCC which replace the need for a register only C complier like ROMCC. Now the whole LinuxBIOS C code can be compiled by GCC.
There are few problems remaining. The first thing is I can only use 7 cache lines of cache (448 bytes) reliably in the K8. The access to the 8th cache line is unstable and the access to the 9th cache line hangs the processor. The other problem is the optimize_connection() function for multi-processor configuration runs unstably under CAR. It does not overflow the stack, it's just plain unstable for some reason. So I can only configure the mainboard as Uniprocessor.
Is there anyone has any idea about these problems ? If we can solve these two problems, Cache As Ram can be used routinly for K8 and probably we can try to extend it to some other processors.
YHLu, Do you have any dual K8 EVB with HDT pin out and works "perfectly" under normal (ROMCC) LinuxBIOS ? The ROMCC LinuxBIOS deos not work for the AMD Serenade board 100% (I still have the phantom device s problem) and the s2885 board we have does not have the pin out.
Eric, What is the "effective" or "equalvalent" stack size of ROMCC ? Is 448 bytes of stack adquant for ROMCC "linted" code in general ?
Ollie