Author: stepan Date: Tue Apr 6 21:50:21 2010 New Revision: 5359 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5359
Log: No warnings day, next round.
Signed-off-by: Stefan Reinauer stepan@coresystems.de Acked-by: Stefan Reinauer stepan@coresystems.de
Modified: trunk/src/Kconfig trunk/src/cpu/amd/model_10xxx/init_cpus.c trunk/src/cpu/amd/model_fxx/model_fxx_init.c trunk/src/cpu/amd/model_lx/cpureginit.c trunk/src/cpu/x86/mtrr/earlymtrr.c trunk/src/include/cpu/x86/cache.h trunk/src/include/cpu/x86/mtrr.h trunk/src/mainboard/amd/mahogany_fam10/romstage.c trunk/src/mainboard/amd/serengeti_cheetah/romstage.c trunk/src/mainboard/asus/a8n_e/mptable.c trunk/src/mainboard/asus/a8n_e/romstage.c trunk/src/mainboard/asus/a8v-e_se/romstage.c trunk/src/mainboard/intel/d945gclf/Makefile.inc trunk/src/mainboard/kontron/986lcd-m/Makefile.inc trunk/src/mainboard/roda/rk886ex/Makefile.inc trunk/src/mainboard/tyan/s4880/romstage.c trunk/src/northbridge/amd/amdk8/amdk8_f.h trunk/src/northbridge/amd/amdk8/misc_control.c trunk/src/northbridge/amd/amdk8/raminit.c trunk/src/northbridge/amd/amdk8/raminit_f.c trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c trunk/src/northbridge/amd/lx/raminit.c trunk/src/southbridge/amd/amd8111/amd8111_early_ctrl.c trunk/src/southbridge/amd/cs5536/cs5536_ide.c trunk/src/southbridge/amd/rs780/rs780_early_setup.c trunk/src/southbridge/amd/sb700/sb700_smbus.c trunk/src/southbridge/amd/sb700/sb700_smbus.h trunk/src/southbridge/via/vt8237r/vt8237_fadt.c
Modified: trunk/src/Kconfig ============================================================================== --- trunk/src/Kconfig Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/Kconfig Tue Apr 6 21:50:21 2010 (r5359) @@ -621,7 +621,8 @@ depends on (SOUTHBRIDGE_VIA_VT8237R \ || NORTHBRIDGE_VIA_VX800 \ || NORTHBRIDGE_VIA_CX700 \ - || NORTHBRIDGE_AMD_AMDK8) + || NORTHBRIDGE_AMD_AMDK8 \ + || NORTHBRIDGE_AMD_AMDFAM10) help This option enables additional SMBus (and SPD) debug messages.
Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/init_cpus.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/cpu/amd/model_10xxx/init_cpus.c Tue Apr 6 21:50:21 2010 (r5359) @@ -91,7 +91,7 @@ wrmsr(0xc0010058, msr); // MMIO Config Base Address Reg
//mtrr for that range? -// set_var_mtrr_x(7, PCI_MMIO_BASE<<8, PCI_MMIO_BASE>>(32-8), 0x00000000, 0x01, MTRR_TYPE_UNCACHEABLE); + // set_var_mtrr_x(7, PCI_MMIO_BASE<<8, PCI_MMIO_BASE>>(32-8), 0x00000000, 0x01, MTRR_TYPE_UNCACHEABLE);
set_wrap32dis();
@@ -293,7 +293,7 @@ }
-static void STOP_CAR_AND_CPU() +static void STOP_CAR_AND_CPU(void) { msr_t msr;
@@ -529,7 +529,7 @@ } #endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */
-void AMD_Errata281(u8 node, u32 revision, u32 platform) +static void AMD_Errata281(u8 node, u32 revision, u32 platform) { /* Workaround for Transaction Scheduling Conflict in * Northbridge Cross Bar. Implement XCS Token adjustment @@ -591,7 +591,7 @@ }
-void AMD_Errata298(void) +static void AMD_Errata298(void) { /* Workaround for L2 Eviction May Occur during operation to * set Accessed or dirty bit.
Modified: trunk/src/cpu/amd/model_fxx/model_fxx_init.c ============================================================================== --- trunk/src/cpu/amd/model_fxx/model_fxx_init.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/cpu/amd/model_fxx/model_fxx_init.c Tue Apr 6 21:50:21 2010 (r5359) @@ -244,7 +244,6 @@ static void init_ecc_memory(unsigned node_id) { unsigned long startk, begink, endk; - unsigned long hole_startk = 0; unsigned long basek; struct mtrr_state mtrr_state;
@@ -291,6 +290,8 @@ endk = ((pci_read_config32(f1_dev, 0x44 + (node_id*8)) & 0xffff0000) >> 2) + 0x4000;
#if CONFIG_HW_MEM_HOLE_SIZEK != 0 + unsigned long hole_startk = 0; + #if CONFIG_K8_REV_F_SUPPORT == 0 if (!is_cpu_pre_e0()) {
Modified: trunk/src/cpu/amd/model_lx/cpureginit.c ============================================================================== --- trunk/src/cpu/amd/model_lx/cpureginit.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/cpu/amd/model_lx/cpureginit.c Tue Apr 6 21:50:21 2010 (r5359) @@ -25,7 +25,7 @@ ;* SetDelayControl ;* ;*************************************************************************/ -void SetDelayControl(void) +static void SetDelayControl(void) { unsigned int msrnum, glspeed; unsigned char spdbyte0, spdbyte1;
Modified: trunk/src/cpu/x86/mtrr/earlymtrr.c ============================================================================== --- trunk/src/cpu/x86/mtrr/earlymtrr.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/cpu/x86/mtrr/earlymtrr.c Tue Apr 6 21:50:21 2010 (r5359) @@ -4,37 +4,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h>
-/* Validate CONFIG_XIP_ROM_SIZE and CONFIG_XIP_ROM_BASE */ -#if defined(CONFIG_XIP_ROM_SIZE) && !defined(CONFIG_XIP_ROM_BASE) -# error "CONFIG_XIP_ROM_SIZE without CONFIG_XIP_ROM_BASE" -#endif -#if defined(CONFIG_XIP_ROM_BASE) && !defined(CONFIG_XIP_ROM_SIZE) -# error "CONFIG_XIP_ROM_BASE without CONFIG_XIP_ROM_SIZE" -#endif -#if !defined(CONFIG_RAMTOP) -# error "CONFIG_RAMTOP not defined" -#endif - -#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0) -# error "CONFIG_XIP_ROM_SIZE is not a power of 2" -#endif -#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_BASE % CONFIG_XIP_ROM_SIZE) != 0) -# error "CONFIG_XIP_ROM_BASE is not a multiple of CONFIG_XIP_ROM_SIZE" -#endif - -#if (CONFIG_RAMTOP & (CONFIG_RAMTOP -1)) != 0 -# error "CONFIG_RAMTOP must be a power of 2" -#endif - -#if defined(CONFIG_XIP_ROM_SIZE) -# if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK - extern unsigned long AUTO_XIP_ROM_BASE; -# define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE -# else -# define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE -# endif -#endif - +#if 0 static void disable_var_mtrr(unsigned reg) { /* The invalid bit is kept in the mask so we simply @@ -45,6 +15,7 @@ zero.lo = zero.hi = 0; wrmsr(MTRRphysMask_MSR(reg), zero); } +#endif
static void set_var_mtrr( unsigned reg, unsigned base, unsigned size, unsigned type) @@ -61,6 +32,7 @@ wrmsr(MTRRphysMask_MSR(reg), maskm); }
+#if 0 static void set_var_mtrr_x( unsigned reg, uint32_t base_lo, uint32_t base_hi, uint32_t size_lo, uint32_t size_hi, unsigned type)
@@ -79,6 +51,7 @@ } wrmsr(MTRRphysMask_MSR(reg), maskm); } +#endif
static void cache_lbmem(int type) {
Modified: trunk/src/include/cpu/x86/cache.h ============================================================================== --- trunk/src/include/cpu/x86/cache.h Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/include/cpu/x86/cache.h Tue Apr 6 21:50:21 2010 (r5359) @@ -1,3 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Eric W. Biederman + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #ifndef CPU_X86_CACHE #define CPU_X86_CACHE
@@ -17,6 +36,7 @@ { asm volatile("invd" ::: "memory"); } + static inline void wbinvd(void) { asm volatile ("wbinvd");
Modified: trunk/src/include/cpu/x86/mtrr.h ============================================================================== --- trunk/src/include/cpu/x86/mtrr.h Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/include/cpu/x86/mtrr.h Tue Apr 6 21:50:21 2010 (r5359) @@ -31,7 +31,6 @@ #define MTRRfix4K_F0000_MSR 0x26e #define MTRRfix4K_F8000_MSR 0x26f
- #if !defined (ASSEMBLY) && !defined(__PRE_RAM__) #include <device/device.h> void enable_fixed_mtrr(void); @@ -42,5 +41,39 @@ void x86_setup_fixed_mtrrs(void); #endif
+/* Validate CONFIG_XIP_ROM_SIZE and CONFIG_XIP_ROM_BASE */ +#if defined(CONFIG_XIP_ROM_SIZE) && !defined(CONFIG_XIP_ROM_BASE) +# error "CONFIG_XIP_ROM_SIZE without CONFIG_XIP_ROM_BASE" +#endif +#if defined(CONFIG_XIP_ROM_BASE) && !defined(CONFIG_XIP_ROM_SIZE) +# error "CONFIG_XIP_ROM_BASE without CONFIG_XIP_ROM_SIZE" +#endif +#if !defined(CONFIG_RAMTOP) +# error "CONFIG_RAMTOP not defined" +#endif + +#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0) +# error "CONFIG_XIP_ROM_SIZE is not a power of 2" +#endif +#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_BASE % CONFIG_XIP_ROM_SIZE) != 0) +# error "CONFIG_XIP_ROM_BASE is not a multiple of CONFIG_XIP_ROM_SIZE" +#endif + +#if (CONFIG_RAMTOP & (CONFIG_RAMTOP -1)) != 0 +# error "CONFIG_RAMTOP must be a power of 2" +#endif + + +#if !defined (ASSEMBLY) +#if defined(CONFIG_XIP_ROM_SIZE) +# if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK + extern unsigned long AUTO_XIP_ROM_BASE; +# define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE +# else +# define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE +# endif +#endif + +#endif
#endif /* CPU_X86_MTRR_H */
Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/romstage.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c Tue Apr 6 21:50:21 2010 (r5359) @@ -58,18 +58,13 @@ #include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h> -#if 0 -void die(const char *msg); -int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); -#define printk(BIOS_EMERG, fmt, arg...) do_printk(BIOS_EMERG ,fmt, ##arg) -#endif -#define printk(BIOS_INFO, fmt, arg...) do_printk(BIOS_INFO ,fmt, ##arg) #include "cpu/x86/bist.h"
static int smbus_read_byte(u32 device, u32 address);
#include "superio/ite/it8718f/it8718f_early_serial.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/rs780_early_setup.c"
Modified: trunk/src/mainboard/amd/serengeti_cheetah/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Tue Apr 6 21:50:21 2010 (r5359) @@ -29,20 +29,11 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c"
-#if 0 -static void post_code(uint8_t value) { -#if 1 - int i; - for(i=0;i<0x80000;i++) { - outb(value, 0x80); - } -#endif -} -#endif #include "pc80/serial.c" #include "console/console.c" #include <cpu/amd/model_fxx_rev.h> #include "southbridge/amd/amd8111/amd8111_early_smbus.c" +#include <reset.h> #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c"
@@ -54,7 +45,8 @@ #include "lib/delay.c"
#include "northbridge/amd/amdk8/debug.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include <cpu/amd/mtrr.h> #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
Modified: trunk/src/mainboard/asus/a8n_e/mptable.c ============================================================================== --- trunk/src/mainboard/asus/a8n_e/mptable.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/mainboard/asus/a8n_e/mptable.c Tue Apr 6 21:50:21 2010 (r5359) @@ -41,7 +41,7 @@ static const char productid[12] = "A8N-E "; struct mp_config_table *mc; unsigned sbdn; - int i, bus_num; + int bus_num;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc));
Modified: trunk/src/mainboard/asus/a8n_e/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8n_e/romstage.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/mainboard/asus/a8n_e/romstage.c Tue Apr 6 21:50:21 2010 (r5359) @@ -96,7 +96,6 @@
static void sio_setup(void) { - unsigned value; uint32_t dword; uint8_t byte;
Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/romstage.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/mainboard/asus/a8v-e_se/romstage.c Tue Apr 6 21:50:21 2010 (r5359) @@ -187,7 +187,6 @@ int needs_reset = 0; struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - char *p;
sio_init(); w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
Modified: trunk/src/mainboard/intel/d945gclf/Makefile.inc ============================================================================== --- trunk/src/mainboard/intel/d945gclf/Makefile.inc Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/mainboard/intel/d945gclf/Makefile.inc Tue Apr 6 21:50:21 2010 (r5359) @@ -17,11 +17,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-## -## This mainboard requires DCACHE_AS_RAM enabled. It won't work without. -## - obj-y += rtl8168.o
- smmobj-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.o
Modified: trunk/src/mainboard/kontron/986lcd-m/Makefile.inc ============================================================================== --- trunk/src/mainboard/kontron/986lcd-m/Makefile.inc Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/mainboard/kontron/986lcd-m/Makefile.inc Tue Apr 6 21:50:21 2010 (r5359) @@ -17,11 +17,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-## -## This mainboard requires DCACHE_AS_RAM enabled. It won't work without. -## - obj-y += rtl8168.o
- smmobj-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.o
Modified: trunk/src/mainboard/roda/rk886ex/Makefile.inc ============================================================================== --- trunk/src/mainboard/roda/rk886ex/Makefile.inc Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/mainboard/roda/rk886ex/Makefile.inc Tue Apr 6 21:50:21 2010 (r5359) @@ -17,13 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-## -## This mainboard requires DCACHE_AS_RAM enabled. It won't work without. -## - obj-y += m3885.o obj-y += ec.o obj-y += rtl8168.o
- smmobj-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.o
Modified: trunk/src/mainboard/tyan/s4880/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s4880/romstage.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/mainboard/tyan/s4880/romstage.c Tue Apr 6 21:50:21 2010 (r5359) @@ -56,7 +56,6 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_HUB 0x18 - int ret; unsigned device=(ctrl->channel0[0])>>8; smbus_write_byte(SMBUS_HUB, 0x01, device); smbus_write_byte(SMBUS_HUB, 0x03, 0);
Modified: trunk/src/northbridge/amd/amdk8/amdk8_f.h ============================================================================== --- trunk/src/northbridge/amd/amdk8/amdk8_f.h Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/northbridge/amd/amdk8/amdk8_f.h Tue Apr 6 21:50:21 2010 (r5359) @@ -520,6 +520,8 @@
#include <reset.h>
+#if ((CONFIG_MEM_TRAIN_SEQ != 1) && defined(__PRE_RAM__)) || \ + ((CONFIG_MEM_TRAIN_SEQ == 1) && !defined(__PRE_RAM__)) static void wait_all_core0_mem_trained(struct sys_info *sysinfo) {
@@ -585,5 +587,6 @@ }
} +#endif
#endif /* AMDK8_F_H */
Modified: trunk/src/northbridge/amd/amdk8/misc_control.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/misc_control.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/northbridge/amd/amdk8/misc_control.c Tue Apr 6 21:50:21 2010 (r5359) @@ -110,7 +110,7 @@ { uint32_t cmd, cmd_ref; int needs_reset; - struct device *f0_dev, *f2_dev; + struct device *f0_dev; printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. "); needs_reset = 0; @@ -161,6 +161,7 @@ } } else if(is_cpu_pre_d0()) { + struct device *f2_dev; uint32_t dcl; f2_dev = dev_find_slot(0, dev->path.pci.devfn - 3 + 2); /* Errata 98
Modified: trunk/src/northbridge/amd/amdk8/raminit.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/northbridge/amd/amdk8/raminit.c Tue Apr 6 21:50:21 2010 (r5359) @@ -18,10 +18,6 @@ #define QRANK_DIMM_SUPPORT 0 #endif
-#if defined (__GNUC__) -static void hard_reset(void); -#endif - static void setup_resource_map(const unsigned int *register_values, int max) { int i;
Modified: trunk/src/northbridge/amd/amdk8/raminit_f.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit_f.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/northbridge/amd/amdk8/raminit_f.c Tue Apr 6 21:50:21 2010 (r5359) @@ -707,12 +707,14 @@ printk(BIOS_SPEW, "done.\n"); }
+#if 0 static int is_dual_channel(const struct mem_controller *ctrl) { uint32_t dcl; dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); return dcl & DCL_Width128; } +#endif
static int is_opteron(const struct mem_controller *ctrl) { @@ -727,6 +729,7 @@ return !!(nbcap & NBCAP_128Bit); }
+#if 0 static int is_registered(const struct mem_controller *ctrl) { /* Test to see if we are dealing with registered SDRAM. @@ -737,7 +740,7 @@ dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); return !(dcl & DCL_UnBuffDimm); } - +#endif
static void spd_get_dimm_size(unsigned device, struct dimm_size *sz) { @@ -2481,6 +2484,7 @@ pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); }
+#if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */ static void set_SlowAccessMode(const struct mem_controller *ctrl) { uint32_t dch; @@ -2491,6 +2495,7 @@
pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); } +#endif
/* DRAM_OUTPUT_DRV_COMP_CTRL 0, 0x20
Modified: trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c Tue Apr 6 21:50:21 2010 (r5359) @@ -1872,6 +1872,7 @@ return pos; }
+#if CONFIG_MEM_TRAIN_SEQ == 0 static int dqs_save_MC_NVRAM_ch(unsigned int dev, int ch, int pos) { /* 30 bytes per channel */ @@ -1902,6 +1903,7 @@ reg = pci_read_config32(dev, DRAM_CONFIG_HIGH); pos = s3_save_nvram_early(reg, 4, pos); } +#endif
static void dqs_restore_MC_NVRAM(unsigned int dev) {
Modified: trunk/src/northbridge/amd/lx/raminit.c ============================================================================== --- trunk/src/northbridge/amd/lx/raminit.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/northbridge/amd/lx/raminit.c Tue Apr 6 21:50:21 2010 (r5359) @@ -35,7 +35,7 @@ print_debug("======================================\n"); }
-void hcf(void) +static void hcf(void) { print_emerg("DIE\n"); /* this guarantees we flush the UART fifos (if any) and also
Modified: trunk/src/southbridge/amd/amd8111/amd8111_early_ctrl.c ============================================================================== --- trunk/src/southbridge/amd/amd8111/amd8111_early_ctrl.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/southbridge/amd/amd8111/amd8111_early_ctrl.c Tue Apr 6 21:50:21 2010 (r5359) @@ -35,7 +35,7 @@ enable_cf9_x(sbbusn, sbdn); }
-static void hard_reset(void) +void hard_reset(void) { set_bios_reset(); /* reset */ @@ -68,7 +68,7 @@
}
-static void soft_reset(void) +void soft_reset(void) {
unsigned sblk = get_sblk();
Modified: trunk/src/southbridge/amd/cs5536/cs5536_ide.c ============================================================================== --- trunk/src/southbridge/amd/cs5536/cs5536_ide.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/southbridge/amd/cs5536/cs5536_ide.c Tue Apr 6 21:50:21 2010 (r5359) @@ -46,13 +46,6 @@ pci_write_config32(dev, IDE_CFG, ide_cfg); }
-static void ide_enable(struct device *dev) -{ - - printk(BIOS_SPEW, "cs5536_ide: %s\n", __func__); - -} - static struct device_operations ide_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources,
Modified: trunk/src/southbridge/amd/rs780/rs780_early_setup.c ============================================================================== --- trunk/src/southbridge/amd/rs780/rs780_early_setup.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/southbridge/amd/rs780/rs780_early_setup.c Tue Apr 6 21:50:21 2010 (r5359) @@ -371,10 +371,9 @@ #endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 != 1 */
#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 /* save some spaces */ -void fam10_optimization(void) +static void fam10_optimization(void) { device_t cpu_f0, cpu_f2, cpu_f3; - msr_t msr; u32 val;
printk(BIOS_INFO, "fam10_optimization()\n"); @@ -634,16 +633,16 @@ }
/* enable CFG access to Dev8, which is the SB P2P Bridge */ -static void enable_rs780_dev8() +static void enable_rs780_dev8(void) { set_nbmisc_enable_bits(PCI_DEV(0, 0, 0), 0x00, 1 << 6, 1 << 6); }
-static void rs780_before_pci_init() +static void rs780_before_pci_init(void) { }
-static void rs780_early_setup() +static void rs780_early_setup(void) { device_t nb_dev = PCI_DEV(0, 0, 0); printk(BIOS_INFO, "rs780_early_setup()\n");
Modified: trunk/src/southbridge/amd/sb700/sb700_smbus.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_smbus.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/southbridge/amd/sb700/sb700_smbus.c Tue Apr 6 21:50:21 2010 (r5359) @@ -205,7 +205,7 @@ /* space = 0: AX_INDXC, AX_DATAC * space = 1: AX_INDXP, AX_DATAP */ -static void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, +static inline void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val) { u32 tmp;
Modified: trunk/src/southbridge/amd/sb700/sb700_smbus.h ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_smbus.h Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/southbridge/amd/sb700/sb700_smbus.h Tue Apr 6 21:50:21 2010 (r5359) @@ -20,8 +20,6 @@ #ifndef SB700_SMBUS_H #define SB700_SMBUS_H
-//#include <stdint.h> - #define SMBHSTSTAT 0x0 #define SMBSLVSTAT 0x1 #define SMBHSTCTRL 0x2
Modified: trunk/src/southbridge/via/vt8237r/vt8237_fadt.c ============================================================================== --- trunk/src/southbridge/via/vt8237r/vt8237_fadt.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/southbridge/via/vt8237r/vt8237_fadt.c Tue Apr 6 21:50:21 2010 (r5359) @@ -51,8 +51,8 @@ memcpy(header->asl_compiler_id, "CORE", 4); header->asl_compiler_revision = 42;
- fadt->firmware_ctrl = facs; - fadt->dsdt = dsdt; + fadt->firmware_ctrl = (u32)facs; + fadt->dsdt = (u32)dsdt; fadt->preferred_pm_profile = 0; fadt->sci_int = 9; fadt->smi_cmd = 0; @@ -108,9 +108,9 @@ fadt->reset_reg.addrh = 0x0;
fadt->reset_value = 0; - fadt->x_firmware_ctl_l = facs; + fadt->x_firmware_ctl_l = (u32)facs; fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = dsdt; + fadt->x_dsdt_l = (u32)dsdt; fadt->x_dsdt_h = 0;
fadt->x_pm1a_evt_blk.space_id = 1;