On 27.01.20 23:01, Jonathan Zhang (Infra) wrote:
On 1/27/20, 10:56 AM, "Nico Huber" firstname.lastname@example.org wrote:
We had this before: Something that nobody really cared about was upstreamed. And then later, it was copied for newer platforms and people were confused by the feedback that they didn't get for the original platform's code (they expected that what was acceptable for the platform that nobody cared about would always be accepted). I'm not saying that this is the wrong way. Just that from my point of view, we had bad experience with it.
Most industry projects fail in the end. I hope this one does not. Let's work together to make it happens.
I think we are caught in a loop. How can we work together if only you have the blob?
The difficulty is not just at technology side, it is more on the process side and business side. There is a chicken and egg problems between coreboot support for Xeon-SP and FSP support for Xeon-SP. I hope the community is sensitive to the engineers working in silicon vendor. Let's encourage them and support them, it is not easy to turn around a big ship.
So, the first code would just be in the coreboot repository to raise a flag there? So people (at Intel) can see it, not use it?
This seems critical to me. With little documentation (if any at all) about the silicon initialization, no documentation about the blob (I assume?) and no binaries to at least test it, what do you expect from the review?
Without coreboot able to support Xeon-SP, silicon vendor is rightly hesitate to make Xeon-SP FSP as a product. Instead of wishing others to do something, let's firm up coreboot support, and we have allies helping us.
Here I see another company that wants Intel to write firmware. I'm not convinced that is a good idea. Have you evaluated alternatives? If one looks close at Intel's reference code, it's clear that it's mostly boilerplate. Writing new code could considerably reduce its complexity and make things much easier. After a few years with FSP, I'm convinced that writing clean code would be cheaper than the FSP integration with all its avoidable complexity. Intel might not like it, but you could reach proper coreboot support much faster without FSP.