Ricardo Martins (rasmartins@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1168
-gerrit
commit bbe21b5c3d7625a2a3d6417d3b844884ebd84eeb Author: Ricardo Martins rasmartins@gmail.com Date: Wed Jul 4 03:09:49 2012 +0100
IEI PM-LX-800-R11: Added preliminary mainboard support
Details for this board are available at http://www.ieiworld.com/product_groups/industrial/content.aspx?gid=000010000...
Most of the functionality provided by the original BIOS is implemented.
Change-Id: Id9eb10a2f9e49377ea587bddadbba7d76223a715 Signed-off-by: Ricardo Martins rasmartins@gmail.com --- src/mainboard/iei/Kconfig | 3 + src/mainboard/iei/pm-lx-800-r11/Kconfig | 67 +++++++ src/mainboard/iei/pm-lx-800-r11/chip.h | 23 +++ src/mainboard/iei/pm-lx-800-r11/devicetree.cb | 101 +++++++++++ src/mainboard/iei/pm-lx-800-r11/irq_tables.c | 228 +++++++++++++++++++++++++ src/mainboard/iei/pm-lx-800-r11/mainboard.c | 25 +++ src/mainboard/iei/pm-lx-800-r11/romstage.c | 88 ++++++++++ 7 files changed, 535 insertions(+), 0 deletions(-)
diff --git a/src/mainboard/iei/Kconfig b/src/mainboard/iei/Kconfig index 15d93d7..ea26922 100644 --- a/src/mainboard/iei/Kconfig +++ b/src/mainboard/iei/Kconfig @@ -29,6 +29,8 @@ config BOARD_IEI_NOVA_4899R bool "NOVA-4899R" config BOARD_IEI_PCISA_LX_800_R10 bool "PCISA LX-800-R10" +config BOARD_IEI_PM_LX_800_R11 + bool "PM LX-800-R11"
endchoice
@@ -36,6 +38,7 @@ source "src/mainboard/iei/juki-511p/Kconfig" source "src/mainboard/iei/kino-780am2-fam10/Kconfig" source "src/mainboard/iei/nova4899r/Kconfig" source "src/mainboard/iei/pcisa-lx-800-r10/Kconfig" +source "src/mainboard/iei/pm-lx-800-r11/Kconfig"
config MAINBOARD_VENDOR string diff --git a/src/mainboard/iei/pm-lx-800-r11/Kconfig b/src/mainboard/iei/pm-lx-800-r11/Kconfig new file mode 100644 index 0000000..2c8675d --- /dev/null +++ b/src/mainboard/iei/pm-lx-800-r11/Kconfig @@ -0,0 +1,67 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Ricardo Martins rasmartins@gmail.com +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +if BOARD_IEI_PM_LX_800_R11 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_X86 + select CPU_AMD_GEODE_LX + select NORTHBRIDGE_AMD_LX + select SOUTHBRIDGE_AMD_CS5536 + select SUPERIO_WINBOND_W83627EHG + select HAVE_PIRQ_TABLE + select PIRQ_ROUTE + select BOARD_ROMSIZE_KB_512 + select POWER_BUTTON_FORCE_ENABLE + +config MAINBOARD_DIR + string + default iei/pm-lx-800-r11 + +config MAINBOARD_PART_NUMBER + string + default "PM-LX-800-R11" + +config IRQ_SLOT_COUNT + int + default 7 + +choice + prompt "Core/GLIU Frequency" + default CORE_GLIU_500_266 + +config CORE_GLIU_500_266 + bool "500MHz / 266MHz" + +config CORE_GLIU_500_333 + bool "500MHz / 333MHz" + +config CORE_GLIU_500_400 + bool "500MHz / 400MHz" + +endchoice + +config CORE_GLIU + int + default 7 + +endif # BOARD_IEI_PM_LX_800_R11 diff --git a/src/mainboard/iei/pm-lx-800-r11/chip.h b/src/mainboard/iei/pm-lx-800-r11/chip.h new file mode 100644 index 0000000..d69f9b6 --- /dev/null +++ b/src/mainboard/iei/pm-lx-800-r11/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Ricardo Martins rasmartins@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/iei/pm-lx-800-r11/devicetree.cb b/src/mainboard/iei/pm-lx-800-r11/devicetree.cb new file mode 100644 index 0000000..c277606 --- /dev/null +++ b/src/mainboard/iei/pm-lx-800-r11/devicetree.cb @@ -0,0 +1,101 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Ricardo Martins rasmartins@gmail.com +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +chip northbridge/amd/lx + device pci_domain 0 on + device pci 1.0 on end # Northbridge + device pci 1.1 on end # Video Adapter + device pci 1.2 on end # AES Security Block + chip southbridge/amd/cs5536 + register "lpc_serirq_enable" = "0x0000115a" + register "lpc_serirq_polarity" = "0x0000eea5" + register "lpc_serirq_mode" = "1" + register "enable_gpio_int_route" = "0x0d0c0700" + register "enable_ide_nand_flash" = "0" + register "enable_USBP4_device" = "0" # 0:host, 1:device + register "enable_USBP4_overcurrent" = "0" + register "com1_enable" = "1" # CN10 (RS422/486 COM3) + register "com1_address" = "0x3e8" + register "com1_irq" = "5" + register "com2_enable" = "0" + register "unwanted_vpci[0]" = "0" # End of list has a zero + device pci e.0 on end # RTL8100C + device pci f.0 on # ISA Bridge + chip superio/winbond/w83627ehg # Winbond W83627EHG + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + + device pnp 2e.5 on # PS/2 keyboard/mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # Keyboard + irq 0x72 = 12 # Mouse + end + + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 0 + end + + device pnp 2e.6 off end # Serial Flash Interface + device pnp 2e.7 off end # GPIO1, GPIO6, Game Port & MIDI Port + device pnp 2e.8 off end # WDTO# & PLED + device pnp 2e.9 off end # GPIO2,GPIO3, GPIO4, GPIO5 & SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.106 off end # + device pnp 2e.107 off end # + device pnp 2e.207 off end # + + end + end + device pci f.2 on end # IDE Controller + device pci f.3 off end # Audio (N/A) + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + end + end + + # APIC cluster is late CPU init. + device lapic_cluster 0 on + chip cpu/amd/geode_lx + device lapic 0 on end + end + end +end diff --git a/src/mainboard/iei/pm-lx-800-r11/irq_tables.c b/src/mainboard/iei/pm-lx-800-r11/irq_tables.c new file mode 100644 index 0000000..e3c9f18 --- /dev/null +++ b/src/mainboard/iei/pm-lx-800-r11/irq_tables.c @@ -0,0 +1,228 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Ricardo Martins rasmartins@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/pci_ids.h> +#include <arch/pirq_routing.h> + +/* Platform IRQs */ +#define PIRQA 10 +#define PIRQB 11 +#define PIRQC 11 +#define PIRQD 11 + +/* Links */ +#define L_PIRQA 1 +#define L_PIRQB 2 +#define L_PIRQC 3 +#define L_PIRQD 4 + +/* Bitmaps */ +#define B_LINK0 (1 << PIRQA) +#define B_LINK1 (1 << PIRQB) +#define B_LINK2 (1 << PIRQC) +#define B_LINK3 (1 << PIRQD) + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + 0x0f << 3, /* Interrupt router dev */ + B_LINK0 | B_LINK1 | B_LINK2 | B_LINK3, /* IRQs devoted exclusively to PCI usage */ + PCI_VENDOR_ID_AMD, /* Vendor */ + PCI_DEVICE_ID_AMD_CS5536_ISA, /* Device */ + 0, /* Miniport */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* Reserved */ + 0xa6, /* Checksum */ + { + [0] = { /* Host bridge */ + .slot = 0x00, + .bus = 0x00, + .devfn = (0x01 << 3) | 0x0, + .irq = { + [0] = { + .link = L_PIRQA, + .bitmap = B_LINK0 + }, + [1] = { + .link = L_PIRQB, + .bitmap = B_LINK1 + }, + [2] = { + .link = L_PIRQC, + .bitmap = B_LINK2 + }, + [3] = { + .link = L_PIRQD, + .bitmap = B_LINK3 + } + } + }, + + [1] = { /* ISA bridge */ + .slot = 0x00, + .bus = 0x00, + .devfn = (0x0f << 3) | 0x0, + .irq = { + [0] = { + .link = L_PIRQA, + .bitmap = B_LINK0 + }, + [1] = { + .link = L_PIRQB, + .bitmap = B_LINK1 + }, + [2] = { + .link = L_PIRQC, + .bitmap = B_LINK2 + }, + [3] = { + .link = L_PIRQD, + .bitmap = B_LINK3 + } + } + }, + + [2] = { /* Ethernet */ + .slot = 0x00, + .bus = 0x00, + .devfn = (0x0e << 3) | 0x0, + .irq = { + [0] = { + .link = L_PIRQD, + .bitmap = B_LINK3 + }, + [1] = { + .link = L_PIRQA, + .bitmap = B_LINK0 + }, + [2] = { + .link = L_PIRQB, + .bitmap = B_LINK1 + }, + [3] = { + .link = L_PIRQC, + .bitmap = B_LINK2 + } + } + }, + + [3] = { /* PCI Connector - Slot 0 */ + .slot = 0x01, + .bus = 0x00, + .devfn = (0x09 << 3) | 0x0, + .irq = { + [0] = { + .link = L_PIRQA, + .bitmap = B_LINK0 + }, + [1] = { + .link = L_PIRQB, + .bitmap = B_LINK1 + }, + [2] = { + .link = L_PIRQC, + .bitmap = B_LINK2 + }, + [3] = { + .link = L_PIRQD, + .bitmap = B_LINK3 + } + } + }, + + [4] = { /* PCI Connector - Slot 1 */ + .slot = 0x02, + .bus = 0x00, + .devfn = (0x0c << 3) | 0x0, + .irq = { + [0] = { + .link = L_PIRQB, + .bitmap = B_LINK1 + }, + [1] = { + .link = L_PIRQC, + .bitmap = B_LINK2 + }, + [2] = { + .link = L_PIRQD, + .bitmap = B_LINK3 + }, + [3] = { + .link = L_PIRQA, + .bitmap = B_LINK0 + } + } + }, + + [5] = { /* PCI Connector - Slot 2 */ + .slot = 0x03, + .bus = 0x00, + .devfn = (0x0b << 3) | 0x0, + .irq = { + [0] = { + .link = L_PIRQC, + .bitmap = B_LINK2 + }, + [1] = { + .link = L_PIRQD, + .bitmap = B_LINK3 + }, + [2] = { + .link = L_PIRQA, + .bitmap = B_LINK0 + }, + [3] = { + .link = L_PIRQB, + .bitmap = B_LINK1 + } + } + }, + + [6] = { /* PCI Connector - Slot 3 */ + .slot = 0x04, + .bus = 0x00, + .devfn = (0x0a << 3) | 0x0, + .irq = { + [0] = { + .link = L_PIRQD, + .bitmap = B_LINK3 + }, + [1] = { + .link = L_PIRQA, + .bitmap = B_LINK0 + }, + [2] = { + .link = L_PIRQB, + .bitmap = B_LINK1 + }, + [3] = { + .link = L_PIRQC, + .bitmap = B_LINK2 + } + } + } + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} diff --git a/src/mainboard/iei/pm-lx-800-r11/mainboard.c b/src/mainboard/iei/pm-lx-800-r11/mainboard.c new file mode 100644 index 0000000..b598cac --- /dev/null +++ b/src/mainboard/iei/pm-lx-800-r11/mainboard.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Ricardo Martins rasmartins@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> + +struct chip_operations mainboard_ops = { + CHIP_NAME("IEI PM-LX-800-R11 Mainboard") +}; diff --git a/src/mainboard/iei/pm-lx-800-r11/romstage.c b/src/mainboard/iei/pm-lx-800-r11/romstage.c new file mode 100644 index 0000000..f756622 --- /dev/null +++ b/src/mainboard/iei/pm-lx-800-r11/romstage.c @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2012 Ricardo Martins rasmartins@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <spd.h> +#include <arch/io.h> +#include <arch/hlt.h> +#include <arch/llshell.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/lxdef.h> +#include <southbridge/amd/cs5536/cs5536.h> +#include <southbridge/amd/cs5536/early_smbus.c> +#include <southbridge/amd/cs5536/early_setup.c> +#include <superio/winbond/w83627ehg/early_serial.c> + +#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) + +static inline int spd_read_byte(unsigned int device, unsigned int address) +{ + /* Only DIMM0 is available. */ + if (device != DIMM0) + return 0xff; + + return smbus_read_byte(device, address); +} + +#if CONFIG_CORE_GLIU_500_400 +# define PLLMSRhi 0x0000059c +#elif CONFIG_CORE_GLIU_500_333 +# define PLLMSRhi 0x0000049c +#else +# define PLLMSRhi 0x0000039c +#endif + +#define PLLMSRlo 0x07de000 + +#include <northbridge/amd/lx/raminit.h> +#include <northbridge/amd/lx/pll_reset.c> +#include <northbridge/amd/lx/raminit.c> +#include <lib/generic_sdram.c> +#include <cpu/amd/geode_lx/cpureginit.c> +#include <cpu/amd/geode_lx/syspreinit.c> +#include <cpu/amd/geode_lx/msrinit.c> + +void main(unsigned long bist) +{ + static const struct mem_controller memctrl[] = { + {.channel0 = {DIMM0, DIMM1}} + }; + + SystemPreInit(); + msr_init(); + + cs5536_early_setup(); + + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + + report_bist_failure(bist); + + pll_reset(1); + + cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); + + sdram_initialize(1, memctrl); +}