Hi, all,
I check the FILO code, all devices work under polling mode. So I think at the very beginning of initialization, OS probably needs the legacy PIC enabled before APIC mode enabled.
Best Regards
??? Feng Libo @ AMD Ext: 20906 Mobile Phone: 13683249071 Office Phone: 0086-010-62801406
-----Original Message----- From: Segher Boessenkool [mailto:segher@kernel.crashing.org] Sent: Wednesday, March 05, 2008 4:10 AM To: Feng, Libo Cc: coreboot@coreboot.org Subject: Re: [coreboot] PIC, APIC, XAPIC and XIOAPIC
In LB stage, only PIC mode is applied, isn't it? However, I remember some people of LB community told me there was no ISR except the debug ISR during LB. So does this mean it totally unnecessary to setup PIC via C00h/C001h IO port in LB?
You need to set up the legacy PIC really early, since it doesn't initialise itself to any sane settings at bootup.
Segher