Hi Nico,
On Tue, May 29, 2018 at 10:24 AM, Nico Huber nico.h@gmx.de wrote:
Hello Hal,
On 28.05.2018 08:06, Hal Martin wrote:
Name Offset Type Size Comp ... cpu_microcode_blob.bin 0x6f00 microcode 0 none
The size looks troubling, I think you really need the correct microcode binary to get into coreboot. Make 100% sure it matches your SKU.
Nice catch! I added the CPU microcode extracted from the original firmware, but unfortunately it hasn't made any difference in the behaviour:
CREATE build/mainboard/compulab/fitlet2/cbfs-file.GH4n6d.out (from /home/ubuntu/coreboot/.config) Created CBFS (capacity = 12179416 bytes) CBFS fallback/romstage CBFS cpu_microcode_blob.bin CBFS fallback/ramstage CBFS config CBFS revision CBFS fspm.bin CBFS fsps.bin CBFS fallback/postcar CBFS fallback/dsdt.aml CBFS fallback/payload DD Adding Intel Firmware Descriptor IFDTOOL Unlocking Management Engine Platform is: aplk File build/coreboot.pre is 16777216 bytes Writing new image to build/coreboot.pre.new CBFS coreboot.rom UPDATE-FIT CBFSLAYOUT coreboot.rom
This image contains the following sections that can be manipulated with this tool:
'SI_DESC' (size 4096, offset 0) 'IFWI' (size 3141632, offset 4096) 'COREBOOT' (CBFS, size 12179456, offset 3147776) 'RECOVERY_MRC_CACHE' (size 65536, offset 15327232) 'RW_MRC_CACHE' (size 65536, offset 15392768) 'RW_VAR_MRC_CACHE' (size 4096, offset 15458304) 'BIOS_UNUSABLE' (size 262144, offset 15462400) 'DEVICE_EXTENSION' (size 1048576, offset 15724544) 'UNUSED_HOLE' (size 4096, offset 16773120)
It is possible to perform either the write action or the CBFS add/remove actions on every section listed above. To see the image's read-only sections as well, rerun with the -w option. CBFSPRINT coreboot.rom
Name Offset Type Size Comp cbfs master header 0x0 cbfs header 32 none fallback/romstage 0x80 stage 31796 none cpu_microcode_blob.bin 0x7d00 microcode 53248 none fallback/ramstage 0x14d80 stage 72798 none config 0x26a40 raw 772 none revision 0x26d80 raw 575 none fspm.bin 0x27000 fsp 364544 none fallback/dsdt.aml 0x80040 raw 99 none (empty) 0x80100 null 1688 none fsps.bin 0x807c0 fsp 172032 none fallback/postcar 0xaa800 stage 21284 none fallback/payload 0xafb80 simple elf 633503 none (empty) 0x14a680 null 10793240 none bootblock 0xb957c0 bootblock 32768 none
Built compulab/fitlet2 (Fitlet2)
Is it expected that ifwitool will not work on the coreboot generated
image?
Or does this indicate I've made a mistake somewhere?
I'm not sure. I'd extract the bios/ifwi region using ifdtool and try to run ifwitool on that.
I've also tried to extract the bios region from the coreboot.rom file and run ifdtool on that, but I get the same error message I receive when running ifdtool on the coreboot.rom:
E: Image does not contain BPDT!! E: ./ifwitool: ifwi parsing failed
More and more I am suspecting that something is wrong with the generated image.
Is it possible to generate a "portable" coreboot image that I could use with the Intel FIT tool to replace the vendor BIOS region?
I am taking the FSP_M and FSP_S from Intel's Apollo Lake FSP repository, but I believe the vendor is using components from AMI for this. Without uart I'm not even sure if I'm getting to memory/silicon init. But maybe it's necessary to use the FSP components from Intel's repository because otherwise coreboot may call functions that don't exist in AMI's version?
Thanks, Hal
Nico