On Mon, 2021-10-04 at 07:32 -0700, ron minnich wrote:
that was pre-git but is there any useful comment in git anyway? I only have the vaguest memory of why it went in.
It was introduced in c84c1906b7 and fcd5ace00b3 without explanation. I particularly don't understand the lapic_write_around and lapic_read_around functions that pop up. From my perspective, none of this is needed and you can just use the usual lapic_read and lapic_write functions.
Julian
On Mon, Oct 4, 2021 at 7:14 AM Julian Stecklina julian.stecklina@cyberus-technology.de wrote:
Hello,
I was looking at the Local APIC code in coreboot and was wondering about `lapic_write_atomic` in src/include/cpu/x86/lapic.h. This uses an atomic XCHG to write to Local APIC registers. I would like to understand why this would be necessary, because none of the OSes I've seen or worked on do anything similar. ALso the Intel SDM discourages acceses that are not plain loads/stores.
In the coreboot code, this function seems to exist for a really long time. I've found this from 2004:
#ifdef CONFIG_X86_GOOD_APIC # define FORCE_READ_AROUND_WRITE 0 # define lapic_read_around(x) lapic_read(x) # define lapic_write_around(x,y) lapic_write((x),(y)) #else # define FORCE_READ_AROUND_WRITE 1 # define lapic_read_around(x) lapic_read(x) # define lapic_write_around(x,y) lapic_write_atomic((x),(y)) #endif
This seems to indicate that using atomic writes was a workaround of some kind. Does anyone know more?
Thanks! Julian