Author: mjones Date: 2008-05-16 20:08:54 +0200 (Fri, 16 May 2008) New Revision: 3329
Modified: trunk/coreboot-v2/src/mainboard/amd/db800/Config.lb trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Config.lb trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Config.lb trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Config.lb Log: Geode platforms that use a LPC Super I/O had the LPC serial IRQ set to all the possible IRQs generated by the SIO. This included IRQ 7 as the default parallel port IRQ. This overlapped with the MFGPT driver setting IRQ7 for it's own use. This fix removes IRQ7 from the serial IRQ list for all the mainboards that were setting it to prevent the conflict and crash when the MFGPT driver loads.
Signed-off-by: Marc Jones marc.jones@amd.com Acked-by: Peter Stuge peter@stuge.se Acked-by: Ronald G. Minnich rminnich@gmail.com
Modified: trunk/coreboot-v2/src/mainboard/amd/db800/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/db800/Config.lb 2008-05-16 15:43:35 UTC (rev 3328) +++ trunk/coreboot-v2/src/mainboard/amd/db800/Config.lb 2008-05-16 18:08:54 UTC (rev 3329) @@ -127,8 +127,8 @@ # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # SIRQ Mode = Active(Quiet) mode. Save power.... # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK - register "lpc_serirq_enable" = "0x000010da" - register "lpc_serirq_polarity" = "0x0000EF25" + register "lpc_serirq_enable" = "0x0000105a" + register "lpc_serirq_polarity" = "0x0000EFA5" register "lpc_serirq_mode" = "1" register "enable_gpio_int_route" = "0x0D0C0700" register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Config.lb 2008-05-16 15:43:35 UTC (rev 3328) +++ trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Config.lb 2008-05-16 18:08:54 UTC (rev 3329) @@ -128,9 +128,9 @@ # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK # How to get these? Boot linux and do this: # rdmsr 0x51400025 - register "lpc_serirq_enable" = "0x000010da" + register "lpc_serirq_enable" = "0x0000105a" # rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits - register "lpc_serirq_polarity" = "0x0000EF25" + register "lpc_serirq_polarity" = "0x0000EFA5" # mode is high 10 bits (determined from code) register "lpc_serirq_mode" = "1" # Don't yet know how to find this.
Modified: trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Config.lb 2008-05-16 15:43:35 UTC (rev 3328) +++ trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Config.lb 2008-05-16 18:08:54 UTC (rev 3329) @@ -78,8 +78,8 @@ # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # SIRQ Mode = Active(Quiet) mode. Save power.... # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK - register "lpc_serirq_enable" = "0x000010da" - register "lpc_serirq_polarity" = "0x0000EF25" + register "lpc_serirq_enable" = "0x0000105a" + register "lpc_serirq_polarity" = "0x0000EFA5" register "lpc_serirq_mode" = "1" register "enable_gpio_int_route" = "0x0D0C0700" register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
Modified: trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Config.lb 2008-05-16 15:43:35 UTC (rev 3328) +++ trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Config.lb 2008-05-16 18:08:54 UTC (rev 3329) @@ -148,9 +148,9 @@ # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK # How to get these? Boot linux and do this: # rdmsr 0x51400025 - register "lpc_serirq_enable" = "0x000010da" + register "lpc_serirq_enable" = "0x0000105a" # rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits - register "lpc_serirq_polarity" = "0x0000EF25" + register "lpc_serirq_polarity" = "0x0000EFA5" # mode is high 10 bits (determined from code) register "lpc_serirq_mode" = "1" # Don't yet know how to find this.