On 13 Jun 2003, Eric W. Biederman wrote:
"Brian G. Rhodes" bgr@gw.linespeed.net writes:
The reason I was not getting interrupts on devices in the pci slot on the EPIA is because they were not set to be bus masters, so they would never generate interrupts. A quick write to the command register fixed the problem. Command register is being set to 0x02. It should be set to 0x06. a 6 to 4.
Actually this is an interesting symptom. Being a Bus Master means you can initiate transactions on the PCI bus i.e. DMA. There is no requirement that I know of that the bus master bit applies to IRQ's. Those are out of band signals.
Seems like a hardware bug to me.
ron