Stefan Reinauer wrote:
]Also, enabling Prefetch and 33MHz fast read mode should possibly go in the ]southbridge's bootblock.c so the first cbfs scan does not run with the ]slow settings.
Hello Stefan,
You are probably right. In fact these settings are applied fairly early even without the patch: tracker.coreboot.org/trac/coreboot/browser/trunk/src/vendorcode/amd/cimx/ sb800/SBPOR.c#L67 (prefetch) tracker.coreboot.org/trac/coreboot/browser/trunk/src/vendorcode/amd/cimx/ sb800/SBPOR.c#L249 (spi speed)
The patch applies the settings even earlier for boot time reduction. The gain is small:
---e350m1 DOS AHCI SSD boot time in ms--- early prefetch off on off on early 33 mhz off off on on --- --- --- --- 686 682 736 679
Together the changes save 7 ms. The question is, where do we draw the line on boot time reduction? I worked in a group a while back where a manager said, "every millisecond counts". This was due to a desire to make a customer's board boot more quickly than a board from a competitor. Certainly no user can notice a boot time difference of a few ms. The difference is easy to measure though, and in some cases a few ms is enough to affect who calls their board fastest. On the other hand, coreboot+seabios is already several thousand ms faster than UEFI, so maybe saving 7 ms is not worth the somewhat out of place code.
Thanks, Scott