Hi Peter,
I'll have a play - I've looked at the TI datasheets for both parts, and concluded that they don't give a sensible idea of when the signal should be asserted and when not. It reads as though other signals control the power to the card and this is an optional power switch, which I suspect may be used by the original BIOS/CE.Net firmware to enable/disable the slot for security reasons (I cannot find mention of this in the manual, but cannot think of any other reason).
Is there any way in coreboot v2 to run something mainboard specific just before starting the payload? I ask because on the T20 I have no output but a bicolour LED connected to the southbridge, and it'd be good to know when execution was about to be passed to the payload and that we'd found RAM etc OK - I tried post ram initialisation in auto.c, however this all happens before coreboot is copied to RAM and executed.
Nick
On Tue, 2008-06-17 at 22:21 +0200, Peter Stuge wrote:
On Tue, Jun 17, 2008 at 10:20:21PM +0200, Peter Stuge wrote:
On Tue, Jun 17, 2008 at 08:11:40PM +0100, Nick Innes wrote:
I'm also a little stumped on the initialisation of the cardbus slot
..
I think the EPIA-MII is a very different animal, but would be thrilled to be wrong and benefit from someone's experiences with it!
EPIA-MII has a Ricoh RL5c456 controller which is really buggy. Linux PCMCIA people have documented a unfixable (IIRC) problem with slot power.
Which controller is in the T30?
Never mind, just read your old post. No idea about the TI controller.
Can you look into that shutdown GPIO?
//Peter