Re: [coreboot] DL145 G1 with dual dualcore CPU using coreboot ?

[Scott Duplichan]

Peter Stuge wrote:

]> // write to AMD 8131 Link Command Register BUID field (bits 16-20)
]> // with value 2 so that the 8111 can be accessed:
]> -epcid 0 0 0 c0 00420008 // bus 0, dev 0, fun 0, reg 0xc0
]
]Is it safe to blindly write this word in
]src/northbridge/amd/amdfam10/bootblock.c ? I think this is what is
]missing.

I am not sure if that is a good enough way or not. It has been
a while since I worked with that generation chipset. This way
also works with simnow:

dev = PCI_DEV(0, 0, 0);
    byte = pci_io_read_config8(dev, 0xc2);
    byte |= 2; /* set BUID in 8131 Link Command Register */
    pci_io_write_config8(dev, 0xc2, byte);

]> // write to AMD 8111 Rom Decode Control Register and set bit 7
]> // to enable LPC memory decoding of the top 4MB of 4GB space:
]> -epcib 0 1 0 43 80 // bus 0, dev 1, fun 0, reg 0x43
]
]This is already done in src/southbridge/amd/amd8111/bootblock.c for
]device id 1022:7468 - is this the correct device for that board?

Oh yes, you are correct. That code runs very early, just a few
instructions after reset. Adding only the above AMD8131 write
lets it find and program the 8111 rom decode. The weird thing
is that in simnow, it runs all the way through then loops in
cbfs. If I remove this line:
    byte |= (1 << 6); /* Enable 0xFFB00000-0xFFBFFFFF (1MB). */
, then it continues. I suspect this is a simnow problem, because
the FFB00000 range decode is needed for programming some LPC
flash chip models.

Thanks,
Scott