Stefan,
This should be a relatively straight forward change to config.g. I would prefer to see the config format maintained, so I would suggest using:
htlink 0 "mc1" speed = 200 width = 8 end
htlink 0 "amd8131-1" end
rather than
htlink 0 "mc1" speed=200 width=8 htlink 0 "amd8131-1"
Let me know if you need any help in implementing it.
Regards,
Greg
At 4:57 PM +0200 12/9/03, Stefan Reinauer wrote:
- ron minnich rminnich@lanl.gov [030912 15:06]:
The config language only supports a parent-child relationship, and HT has a much richer interconnection structure.
Yes. Currently the config tool only allows an acyclic graph for describing hardware. this does not suit the machine description that would be needed for hypertransport.
Are you saying that we should reflect this richer topology that HT has in the config language?
Yes, and I think this does not need to be really complex. See the below example. Then the romimage class could be extended to write a new file htlinks.h in case it detects "htlink" keywords in any device. I'm currently fighting myself a bit through config.g to see how this can be done.
I don't think this necessarily should go to the static device tree, since we would have to use the device tree in romcc code then, which is not yet possible iirc. (And might bloat romcc code up)
typedef struct htlink { int direction; // 0,1,2 for LDT0,1,2 int speed; int width; int nodenum; // ht device number of remote component } htlink_t;
enum { NORTHBRIDGE, SOUTHBRIDGE, PCIBRIDGE, } htdev_t;
typedev struct htdev { htdev_t type; // type int num; // instance, i.e. the num'th device of type "type" htlink_t links[3]; } htdev_t;
htdevs_t **get_htdevs() { htdevt_t htdevs[]={ { NORTHBRIDGE, 0, { { 0, 800, 16, 1 }, { 1, 800, 16, 3 }, { 2, 800, 16, 4 }, // range 0-3 used by cpus } }, { NORTHBRIDGE, 1, { { 0, 800, 16, 0 }, { 1, 800, 16, 5 }, { 2, 800, 16, 3 }, } }, [..] };
return htdevs;
}
generated from a config file like this:
northbridge amd/amdk8 "mc0" pci 0:18.0 pci 0:18.0 pci 0:18.0 pci 0:18.1 pci 0:18.2 pci 0:18.3 htlink 0 "mc1" [ speed=default|200|400.. ] [ width=default|8|16 ] htlink 1 "mc3" speed=default width=16 htlink 2 "amd8111" speed=600 width=8 end
northbridge amd/amdk8 "mc1" pci 0:19.0 pci 0:19.0 pci 0:19.0 pci 0:19.1 pci 0:19.2 pci 0:19.3 htlink 0 "mc0" htlink 1 "amd8131" htlink 2 "mc3" end
northbridge amd/amdk8 "mc2" pci 0:1a.0 pci 0:1a.0 pci 0:1a.0 pci 0:1a.1 pci 0:1a.2 pci 0:1a.3 htlink 0 "mc3" htlink 2 "mc0" end
northbridge amd/amdk8 "mc3" pci 0:1b.0 pci 0:1b.0 pci 0:1b.0 pci 0:1b.1 pci 0:1b.2 pci 0:1b.3 htlink 0 "mc2" htlink 1 "mc1" end
southbridge amd/amd8131 "amd8131-1" pci 0:0.0 pci 0:0.1 pci 0:1.0 pci 0:1.1 htlink 0 "mc0" htlink 1 "amd8131-2" end
southbridge amd/amd8131 "amd8131-2" pci 0:0.0 pci 0:0.1 pci 0:1.0 pci 0:1.1 htlink 0 "amd8131-1" end
southbridge amd/amd8111 "amd8111" pci 0:0.0 pci 0:1.0 pci 0:1.1 pci 0:1.2 pci 0:1.3 pci 0:1.5 pci 0:1.6 superio NSC/pc87360 pnp 1:2e.0 pnp 1:2e.1 pnp 1:2e.2 pnp 1:2e.3 pnp 1:2e.4 pnp 1:2e.5 pnp 1:2e.6 pnp 1:2e.7 pnp 1:2e.8 pnp 1:2e.9 pnp 1:2e.a register "com1" = "{1, 0, 0x3f8, 4}" register "lpt" = "{1}" end htlink 0 "mc0" speed=200 width=8 end
Stefan
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