On Tue, 2 Mar 2010 11:43:42 -0500, Keith Hui buurin@gmail.com wrote:
On Tue, Mar 2, 2010 at 11:22 AM, ron minnich rminnich@gmail.com wrote:
On Tue, Mar 2, 2010 at 5:39 AM, Keith Hui buurin@gmail.com wrote:
ramtest.c:6.0: warning: Replacing undefined macro: CONFIG_SSE2 with 0 ramtest.c:56.0: warning: Replacing undefined macro: CONFIG_SSE2 with 0
This should be fixed in Kconfig. Probibly in the cpu Kconfig?
fix this first. You really want your code to be warning-free.
I did a search, and the only reference (ie. this ramtest.c) is elsewhere
in the code - src/lib/. That may be used by something else.
edosd |= 0x04; // <<< ABORT!did you try just edosd = edosd | 4;
just wondering if it's that simple.
I could try tonight. But I used both notations fearing that romcc
doesn't
support more obscure constructs, and both work in other places.
hmm
That's with the clock chip my board uses. Where should this code be placed?
depends on the chip I assume. Very, very early is my bet.
I'm mean where in the source tree should I put it. Southbridge,
mainboard-specific romstage, or northbridge?
I would say romstage.c just after early_smbus runs.
The vendor BIOS placed the PIIX4E power management device base port at 0xE400, and its SMBus base port at 0xE800. Coreboot has its SMBus base
port
at 0x0F00. If I want to change the base port to match vendor BIOS,
where
should it be made?
Why? We've never seen a need to match these addresses up.
So that when I disassemble my coreboot image, I can look at it side by
side with vendor BIOS and check that it's doing the right thing.
I also don't know if there's anything else in the 0x0F00 port range.
This may also become an issue when the ACPI tables in vendor BIOS gets carried over here and actually gets wired up.
I wouldn't worry to much about ACPI now. You have a ways to go before you get to that point.