You do not know which solution is worse: FSP 1.1, or FSP 2.0?! FSP 1,1 is useless (since many problems in IOTG PED group), and FSP 2.0 is getting more complicated (due to INTEL internal job security protection).
It is on your own peril, folks. I should say, at least FSP 2.0 is easier to crack (IMHO)! ;-)
Zoran
On Wed, May 10, 2017 at 12:36 AM, Leahy, Leroy P leroy.p.leahy@intel.com wrote:
Hi Nico,
The Galileo board also supports both FSP 1.1 and FSP 2.0.
Lee Leahy (425) 881-4919 Intel Corporation Suite 125 2700 - 156th Ave NE Bellevue, WA 98007-6554
-----Original Message----- From: Nico Huber [mailto:nico.h@gmx.de] Sent: Tuesday, May 9, 2017 3:27 PM To: Youness Alaoui kakaroto@kakaroto.homelinux.net; Aaron Durbin < adurbin@google.com> Cc: Alexander Couzens lynxis@fe80.eu; Nico Huber nico.huber@secunet.com; Leahy, Leroy P leroy.p.leahy@intel.com; Duncan Laurie < dlaurie@chromium.org>; coreboot@coreboot.org Subject: Re: [coreboot] Will we maintain Skylake/FSP1.1?
On 09.05.2017 18:47, Youness Alaoui wrote:
I thought FSP 1.1 was for skylake and FSP 2.0 for Kabylake, I didn't realize 2.0 would be compatible with skylake too. Does this mean a skylake port could use fsp 1.1 or 2.0 ? In that case, is the 2.0 version better maintained, more stable, easier to integrate, etc.. or are both 1.1 and 2.0 implementations equivalent at this point?
Yes, the Kaby Lake release should be compatible with Skylake too. I'd expect the resulting coreboot to be feature equivalent. The Kconfig option MAINBOARD_USES_FSP2_0 is not tied to SOC_INTEL_KABYLAKE and there is one board (intel/kunimitsu) that implements both interfaces.
Generally, the FSP 2.0 hook-up looks to be in a better shape, though.
I also don't see the 2.0 release in https://github.com/IntelFsp/FSP/ so I assume getting my hands on it would mean grabbing it from somewhere
else....
It's not released yet and I also struggle to find it. I had access to pre-releases in the Intel Business Portal, but that is gone and I don't know yet what to type into the search box on intel.com to find something useful :-/ Would be great if anyone could give us a pointer.
Nico
Thanks, Youness.
On Tue, May 9, 2017 at 11:19 AM, Aaron Durbin adurbin@google.com
wrote:
On Tue, May 9, 2017 at 10:14 AM, Nico Huber nico.huber@secunet.com wrote:
Hi,
I was walking through the Skylake FSP1.1 support in coreboot and asked myself if it is worth to clean it up and maintain the code? given that the upcoming release of Kabylake FSP should be able to supersede it (I presume it is?). Are there any plans yet to drop it once the next FSP is released? (when will that be anyway?)
I wanted to get rid of it, but Intel claimed they had customers using it still.
Btw. does anybody feel like a maintainer for soc/intel/skylake/?
Personally feel? Or want?
In it's current state it's very hard to use from a mainboard porter's point of view. Many of the selectable Kconfig settings are useless (either don't compile or don't run) for FSP1.1, and there's a `struct pei_data` [1] that seems to be a remnant of compatibility for a dif- ferent blob ;)
That's just an old remnant of passing data around. It could be removed as you annotated isolating those pieces to different structs and/or variables for passing data around. The name is obviously not applicable w.r.t. its current use.
Best regards, Nico
PS. Microcode updates are also missing in the upstream blobs repo. Is that a licensing problem? If I try to download them from Intel, it asks me to click to accept that I'll prevent further distribution. I could prepare a patch to add them but somebody else would have to sign it off.
-- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot