On Tue, 2008-02-26 at 16:19 -0500, joe@smittys.pointclark.net wrote:
+static void do_ram_command(const struct mem_controller *ctrl, uint32_t command, uint32_t addr_offset) +{
<snip> + + /* Read from (DIMM start address + addr_offset). */ + read32(0 + addr_offset); //first offset is always 0 +}
This isn't ready for multiple dimms yet. See the cn700 patch I recently sent (but haven't committed yet, I think it was acked).
Oh you mean this? What do I need to do to adapt it for the i82830?
- /* NOTE: Dual-sided ready */ read32(0 + addr_offset);
- for(i = 0; i < (ARRAY_SIZE(ctrl->channel0) * 2); i++) {
reg8 = pci_read_config8(ctrl->d0f3, 0x40 + i);- if(reg8) read32((reg8 << 26) + addr_offset);
- }
This reads from register 0x40 + i, where 0x40 is the top of the first dimm, and i counts to the max number of dimms. Reg 0x40 contains bits 33:26 of the top address, hence the << 26. So you'd need to adjust both of these to fit the i830's DRB mechanism. If the i830 uses an ugly format like the i810 does, then it may be easier to store the size in scratch registers somewhere after it's calculated, and then use those values instead. Sorry I can't get more specific, I've got to head out to my next service call.
-Corey