Hi Jiming, I can find mrc.cache now.But when I restart the system(pci reset),it will also cause a restart again in fspinit api . log: All threads complete. Scan for option roms
Press F12 for boot menu.
Select boot device:
1. AHCI/1: ST3160813AS ATA-8 Hard-Disk (149 GiBytes) In resume (status=0) In 32bit resume Attempting a hard reboot WARNING - Timeout at i8042_wait_write:50! WARNING - Timeout at i8042_wait_write:50! WARNING - Timeout at i8042_wait_write:50! WARNING - Timeout at i8042_wait_write:50! WARNING - Timeout at i8042_wait_write:50! WARNING - Timeout at i8042_wait_write:50! WARNING - Timeout at i8042_wait_write:50! WARNING - Timeout at i8042_wait_write:50! WARNING - Timeout at i8042_wait_write:50! WARNING - Timeout at i8042_wait_write:50!
coreboot-4.0-6196-gf5bde44-dirty Tue Jun 10 03:30:25 EAT 2014 starting... RTC Init POST: 0x44 POST: 0x47 POST: 0x48 Starting the Intel FSP (early_init) Configure Default UPD Data SPD Addr1: 0xa0 SPD Addr2: 0xa2 Tseg Size: 8 MB MMIO Size: 2048 MB IGD Memory Size: 64 MB Aperture Size: 256 MB GTT Size: 2 MB MIPI/ISP: Enabled Sdio: Enabled Sdcard: Enabled Sata: Enabled SATA Mode: AHCI Lpe: Disabled Lpe mode: PCI SIO Dma 0: Enabled SIO I2C0: Enabled SIO I2C1: Enabled SIO I2C2: Enabled SIO I2C3: Enabled SIO I2C4: Enabled SIO I2C5: Enabled SIO I2C6: Enabled Azalia: Enabled SIO Dma1: Enabled Pwm0 Enabled Pwm1: Enabled Hsuart0: Enabled Hsuart1: Enabled Spi: Enabled eMMC 4.1: Disabled eMMC 4.5: Enabled Xhci: Disabled ..
coreboot-4.0-6196-gf5bde44-dirty Tue Jun 10 03:30:25 EAT 2014 starting... RTC Init POST: 0x44 POST: 0x47 POST: 0x48 Starting the Intel FSP (early_init) Configure Default UPD Data SPD Addr1: 0xa0 SPD Addr2: 0xa2 Tseg Size: 8 MB MMIO Size: 2048 MB IGD Memory Size: 64 MB Aperture Size: 256 MB GTT Size: 2 MB MIPI/ISP: Enabled Sdio: Enabled Sdcard: Enabled Sata: Enabled SATA Mode: AHCI Lpe: Disabled Lpe mode: PCI SIO Dma 0: Enabled SIO I2C0: Enabled SIO I2C1: Enabled SIO I2C2: Enabled SIO I2C3: Enabled SIO I2C4: Enabled SIO I2C5: Enabled SIO I2C6: Enabled Azalia: Enabled SIO Dma1: Enabled Pwm0 Enabled Pwm1: Enabled Hsuart0: Enabled Hsuart1: Enabled Spi: Enabled eMMC 4.1: Disabled eMMC 4.5: Enabled Xhci: Disabled POST: 0x4a romstage_main_continue status: 0 hob_list_ptr: 7ae20000 FSP Status: 0x0 Baytrail Chip Variant: Bay Trail-D (Desktop) MRC v0.90 1 channels of DDR3 @ 1333MHz POST: 0x4b POST: 0x4c POST: 0x4d CBMEM: root @ 7adff000 254 entries. POST: 0x4e
Thanks, Tank
From: Sun, Jiming Date: 2014-06-10 01:31 To: jstkf2012@126.com; coreboot CC: martin.roth; ron minnich Subject: RE: [coreboot] smi handler support for fsp baytrail Hi, Tank,
Can you share your log?
Thanks, Jiming
From: jstkf2012@126.com [mailto:jstkf2012@126.com] Sent: Sunday, June 08, 2014 11:59 PM To: Sun, Jiming; coreboot Cc: martin.roth; ron minnich Subject: Re: [coreboot] smi handler support for fsp baytrail
Hi Jiming, It's ok with configure MrcInitTsegSize = 8M.I can boot ubuntu and windows now ! But when I set MrcInitTsegSize = 8M, anthoer issue happened:we can't find mrc.cache which will cause a restart again in fspinit api when I restart the system(pci reset).
Thanks, Tank EXT:8051
From: Sun, Jiming Date: 2014-06-07 00:15 To: jstkf2012@126.com; coreboot CC: martin.roth; rminnich Subject: Re: [coreboot] smi handler support for fsp baytrail Hi, Tank,
It might be the TSEG size configuration.
In devicetree.cb: register "MrcInitTsegSize" = "TSEG_SIZE_DEFAULT"
By default TSEG_SIZE_DEFAULT is 0. It needs to be set to none 0, such as 8 (TSEG_SIZE_8_MB).
Let us know if this helps.
Jiming
From: jstkf2012@126.com [mailto:jstkf2012@126.com] Sent: Thursday, June 05, 2014 11:48 PM To: coreboot Cc: martin.roth; rminnich Subject: [coreboot] smi handler support for fsp baytrail
Hi all,
What about the smi support for fsp baytrail?When I select HAVE_SMI_HANDLER for fsp baytrail,it will halt at: ERROR: Could not find FSP HOB pointer in CBFS! POST: 0x79 POST: 0x9c ACPI: Writing ACPI tables at f0000. ACPI: * FACS @ 000f0210 Length 40ACPI: * DSDT @ 000f0250 Length 2a89SCI is IRQ9 ACPI: added table 1/32, length now 40 ACPI: * FADT @ 000f2ce0 Length f4ACPI: added table 2/32, length now 44 ACPI: * HPET @ 000f2de0 Length 38 ACPI: added table 3/32, length now 48 ACPI: * MADT @ 000f2e20 Length 6c ACPI: added table 4/32, length now 52 ACPI: * MCFG @ 000f2e90 Length 3c ACPI: Could not find CBMEM GNVS ACPI: Patching up global NVS in DSDT at offset 0x009f -> 000f2ed0
Thanks, Tank