Author: uwe Date: Fri Oct 8 21:24:56 2010 New Revision: 5925 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5925
Log: Round 2 of i82801AX fixes to get it into a usable shape.
- Remove left-overs from more generic code in i82801xx times, and fix register names as needed.
- Simplify IDE init code (and save some ROM space too).
- Simplify PIRQ code.
- Use u8 et al instead of uint8_t everywhere.
- Random other fixes.
Signed-off-by: Uwe Hermann uwe@hermann-uwe.de Acked-by: Uwe Hermann uwe@hermann-uwe.de
Modified: trunk/src/southbridge/intel/i82801ax/chip.h trunk/src/southbridge/intel/i82801ax/i82801ax.c trunk/src/southbridge/intel/i82801ax/i82801ax.h trunk/src/southbridge/intel/i82801ax/i82801ax_ac97.c trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c trunk/src/southbridge/intel/i82801ax/i82801ax_ide.c trunk/src/southbridge/intel/i82801ax/i82801ax_lpc.c trunk/src/southbridge/intel/i82801ax/i82801ax_pci.c trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.c trunk/src/southbridge/intel/i82801ax/i82801ax_usb.c
Modified: trunk/src/southbridge/intel/i82801ax/chip.h ============================================================================== --- trunk/src/southbridge/intel/i82801ax/chip.h Fri Oct 8 18:40:23 2010 (r5924) +++ trunk/src/southbridge/intel/i82801ax/chip.h Fri Oct 8 21:24:56 2010 (r5925) @@ -25,22 +25,16 @@ #ifndef SOUTHBRIDGE_INTEL_I82801AX_CHIP_H #define SOUTHBRIDGE_INTEL_I82801AX_CHIP_H
+#include <stdint.h> + struct southbridge_intel_i82801ax_config { - /** - * Interrupt Routing configuration - * If bit7 is 1, the interrupt is disabled. - */ - uint8_t pirqa_routing; - uint8_t pirqb_routing; - uint8_t pirqc_routing; - uint8_t pirqd_routing; - uint8_t pirqe_routing; - uint8_t pirqf_routing; - uint8_t pirqg_routing; - uint8_t pirqh_routing; + u8 pirqa_routing; + u8 pirqb_routing; + u8 pirqc_routing; + u8 pirqd_routing;
- uint8_t ide0_enable; - uint8_t ide1_enable; + u8 ide0_enable; + u8 ide1_enable; };
extern struct chip_operations southbridge_intel_i82801ax_ops;
Modified: trunk/src/southbridge/intel/i82801ax/i82801ax.c ============================================================================== --- trunk/src/southbridge/intel/i82801ax/i82801ax.c Fri Oct 8 18:40:23 2010 (r5924) +++ trunk/src/southbridge/intel/i82801ax/i82801ax.c Fri Oct 8 21:24:56 2010 (r5925) @@ -27,38 +27,21 @@
void i82801ax_enable(device_t dev) { - unsigned int index = 0; - uint16_t cur_disable_mask, new_disable_mask; + u16 reg16, index; + device_t lpc_dev;
- /* All 82801xx devices should be on bus 0. */ - unsigned int devfn = PCI_DEVFN(0x1f, 0); // LPC - device_t lpc_dev = dev_find_slot(0, devfn); // 0 + /* Search for the 82801AA/AB LPC device (D31:F0) on PCI bus 0. */ + lpc_dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); if (!lpc_dev) return;
- /* We're going to assume, perhaps incorrectly, that if a function - * exists it can be disabled. Workarounds for ICH variants that don't - * follow this should be done by checking the device ID. - */ - if (PCI_SLOT(dev->path.pci.devfn) == 31) { - index = PCI_FUNC(dev->path.pci.devfn); - } else if (PCI_SLOT(dev->path.pci.devfn) == 29) { - index = 8 + PCI_FUNC(dev->path.pci.devfn); - } + index = PCI_FUNC(dev->path.pci.devfn);
- /* Function 0 is a bit of an exception. */ - if (index == 0) { - index = 14; - } - - cur_disable_mask = pci_read_config16(lpc_dev, FUNC_DIS); - new_disable_mask = cur_disable_mask & ~(1 << index); /* Enable it. */ - if (!dev->enabled) { - new_disable_mask |= (1 << index); /* Disable it, if desired. */ - } - if (new_disable_mask != cur_disable_mask) { - pci_write_config16(lpc_dev, FUNC_DIS, new_disable_mask); - } + reg16 = pci_read_config16(lpc_dev, FUNC_DIS); + reg16 &= ~(1 << index); /* Enable device. */ + if (!dev->enabled) + reg16 |= (1 << index); /* Disable device, if desired. */ + pci_write_config16(lpc_dev, FUNC_DIS, reg16); }
struct chip_operations southbridge_intel_i82801ax_ops = {
Modified: trunk/src/southbridge/intel/i82801ax/i82801ax.h ============================================================================== --- trunk/src/southbridge/intel/i82801ax/i82801ax.h Fri Oct 8 18:40:23 2010 (r5924) +++ trunk/src/southbridge/intel/i82801ax/i82801ax.h Fri Oct 8 21:24:56 2010 (r5925) @@ -26,37 +26,36 @@ extern void i82801ax_enable(device_t dev); #endif
+#define SMBUS_IO_BASE 0x0f00 +#define PMBASE_ADDR 0x0400 +#define HPET_ADDR 0xfed00000 + #define PCI_DMA_CFG 0x90 #define SERIRQ_CNTL 0x64 #define GEN_CNTL 0xd0 -#define GEN_STS 0xd4 +#define GEN_STA 0xd4 #define RTC_CONF 0xd8 #define GEN_PMCON_3 0xa4
#define PMBASE 0x40 -#define PMBASE_ADDR 0x0400 /* ACPI Base Address Register */ #define ACPI_CNTL 0x44 +#define ACPI_EN (1 << 4) #define BIOS_CNTL 0x4E -#define GPIO_BASE_ICH0_5 0x58 /* LPC GPIO Base Addr. Reg. (ICH0-ICH5) */ -#define GPIO_BASE_ICH6_9 0x48 /* LPC GPIO Base Address Register (ICH6-ICH9) */ -#define GPIO_CNTL_ICH0_5 0x5C /* LPC GPIO Control Register (ICH0-ICH5) */ -#define GPIO_CNTL_ICH6_9 0x4C /* LPC GPIO Control Register (ICH6-ICH9) */ +#define GPIO_BASE 0x58 /* GPIO Base Address Register */ +#define GPIO_CNTL 0x5C /* GPIO Control Register */ +#define GPIO_EN (1 << 4)
#define PIRQA_ROUT 0x60 #define PIRQB_ROUT 0x61 #define PIRQC_ROUT 0x62 #define PIRQD_ROUT 0x63 -#define PIRQE_ROUT 0x68 -#define PIRQF_ROUT 0x69 -#define PIRQG_ROUT 0x6A -#define PIRQH_ROUT 0x6B
#define FUNC_DIS 0xF2
-#define COM_DEC 0xE0 /* LPC I/F Communication Port Decode Ranges (ICH0-ICH5) */ -#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register (ICH6-ICH9) */ -#define LPC_EN_ICH0_5 0xE6 /* LPC IF Enables Register (ICH0-ICH5) */ -#define LPC_EN_ICH6_9 0x82 /* LPC IF Enables Register (ICH6-ICH9) */ +#define COM_DEC 0xE0 /* LPC I/F Comm. Port Decode Ranges */ +#define LPC_EN 0xE6 /* LPC IF Enables */ + +// TODO: FDC_DEC etc.
#define SBUS_NUM 0x19 #define SUB_BUS_NUM 0x1A @@ -77,14 +76,14 @@ #define RTC_POWER_FAILED (1 << 1) #define SLEEP_AFTER_POWER_FAIL (1 << 0)
-/* PCI Configuration Space (D31:F1) */ +/* IDE Timing registers (IDE_TIM) */ #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */
/* IDE_TIM bits */ #define IDE_DECODE_ENABLE (1 << 15)
-/* PCI Configuration Space (D31:F3) */ +/* SMBus */ #define SMB_BASE 0x20 #define HOSTC 0x40
@@ -93,13 +92,7 @@ #define SMB_SMI_EN (1 << 1) #define HST_EN (1 << 0)
-/* SMBus I/O bits. - * TODO: Does it matter where we put the SMBus IO base, as long as we keep - * consistent and don't interfere with anything else? - */ -/* #define SMBUS_IO_BASE 0x1000 */ -#define SMBUS_IO_BASE 0x0f00 - +/* SMBus I/O registers. */ #define SMBHSTSTAT 0x0 #define SMBHSTCTL 0x2 #define SMBHSTCMD 0x3 @@ -107,14 +100,7 @@ #define SMBHSTDAT0 0x5 #define SMBHSTDAT1 0x6 #define SMBBLKDAT 0x7 -#define SMBTRNSADD 0x9 -#define SMBSLVDATA 0xa -#define SMLINK_PIN_CTL 0xe -#define SMBUS_PIN_CTL 0xf
#define SMBUS_TIMEOUT (10 * 1000 * 100)
-/* HPET, if present */ -#define HPET_ADDR 0xfed00000 - -#endif /* SOUTHBRIDGE_INTEL_I82801AX_I82801AX_H */ +#endif
Modified: trunk/src/southbridge/intel/i82801ax/i82801ax_ac97.c ============================================================================== --- trunk/src/southbridge/intel/i82801ax/i82801ax_ac97.c Fri Oct 8 18:40:23 2010 (r5924) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_ac97.c Fri Oct 8 21:24:56 2010 (r5925) @@ -19,8 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-/* This code should work for all ICH* southbridges with AC97 audio/modem. */ - #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -61,4 +59,3 @@ .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801AB_AC97_MODEM, }; -
Modified: trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c Fri Oct 8 18:40:23 2010 (r5924) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c Fri Oct 8 21:24:56 2010 (r5925) @@ -27,21 +27,10 @@ static void enable_smbus(void) { device_t dev; - uint16_t device_id;
- /* Set the SMBus device statically. */ + /* Set the SMBus device statically (D31:F3). */ dev = PCI_DEV(0x0, 0x1f, 0x3);
- /* Check to make sure we've got the right device. */ - device_id = pci_read_config16(dev, 0x2); - - /* Clear bits 7-4 (the only bits that vary between models). */ - device_id &= 0xff0f; - - if (device_id != 0x2403) { - die("Device not found, Corey probably screwed up!"); - } - /* Set SMBus I/O base. */ pci_write_config32(dev, SMB_BASE, SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
Modified: trunk/src/southbridge/intel/i82801ax/i82801ax_ide.c ============================================================================== --- trunk/src/southbridge/intel/i82801ax/i82801ax_ide.c Fri Oct 8 18:40:23 2010 (r5924) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_ide.c Fri Oct 8 21:24:56 2010 (r5925) @@ -31,33 +31,24 @@
static void ide_init(struct device *dev) { - /* Get the chip configuration */ - config_t *config = dev->chip_info; + u16 reg16; + config_t *conf = dev->chip_info;
- /* Enable IDE devices so the Linux IDE driver will work. */ - uint16_t ideTimingConfig; - - ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI); - ideTimingConfig &= ~IDE_DECODE_ENABLE; - if (!config || config->ide0_enable) { - /* Enable primary IDE interface. */ - ideTimingConfig |= IDE_DECODE_ENABLE; - printk(BIOS_DEBUG, "IDE0: Primary IDE interface is enabled\n"); - } else { - printk(BIOS_INFO, "IDE0: Primary IDE interface is disabled\n"); - } - pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig); - - ideTimingConfig = pci_read_config16(dev, IDE_TIM_SEC); - ideTimingConfig &= ~IDE_DECODE_ENABLE; - if (!config || config->ide1_enable) { - /* Enable secondary IDE interface. */ - ideTimingConfig |= IDE_DECODE_ENABLE; - printk(BIOS_DEBUG, "IDE1: Secondary IDE interface is enabled\n"); - } else { - printk(BIOS_INFO, "IDE1: Secondary IDE interface is disabled\n"); - } - pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig); + reg16 = pci_read_config16(dev, IDE_TIM_PRI); + reg16 &= ~IDE_DECODE_ENABLE; + if (!conf || conf->ide0_enable) + reg16 |= IDE_DECODE_ENABLE; + printk(BIOS_DEBUG, "IDE: %s: %s\n", "Primary IDE interface", + conf->ide0_enable ? "on" : "off"); + pci_write_config16(dev, IDE_TIM_PRI, reg16); + + reg16 = pci_read_config16(dev, IDE_TIM_SEC); + reg16 &= ~IDE_DECODE_ENABLE; + if (!conf || conf->ide1_enable) + reg16 |= IDE_DECODE_ENABLE; + printk(BIOS_DEBUG, "IDE: %s: %s\n", "Primary IDE interface", + conf->ide0_enable ? "on" : "off"); + pci_write_config16(dev, IDE_TIM_SEC, reg16); }
static struct device_operations ide_ops = { @@ -69,17 +60,16 @@ .enable = i82801ax_enable, };
-/* 82801AA */ +/* 82801AA (ICH) */ static const struct pci_driver i82801aa_ide __pci_driver = { .ops = &ide_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = 0x2411, };
-/* 82801AB */ +/* 82801AB (ICH0) */ static const struct pci_driver i82801ab_ide __pci_driver = { .ops = &ide_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = 0x2421, }; -
Modified: trunk/src/southbridge/intel/i82801ax/i82801ax_lpc.c ============================================================================== --- trunk/src/southbridge/intel/i82801ax/i82801ax_lpc.c Fri Oct 8 18:40:23 2010 (r5924) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_lpc.c Fri Oct 8 21:24:56 2010 (r5925) @@ -36,7 +36,7 @@
typedef struct southbridge_intel_i82801ax_config config_t;
-/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control +/* PIRQ[n]_ROUT[3:0] - IRQ Routing (ISA compatible) * 0x00 - 0000 = Reserved * 0x01 - 0001 = Reserved * 0x02 - 0010 = Reserved @@ -53,8 +53,10 @@ * 0x0D - 1101 = Reserved * 0x0E - 1110 = IRQ14 * 0x0F - 1111 = IRQ15 - * PIRQ[n]_ROUT[7] - PIRQ Routing Control - * 0x80 - The PIRQ is not routed. + * + * PIRQ[n]_ROUT[7] - Interrupt Routing Enable (IRQEN) + * 0 - The PIRQ is routed to the ISA-compatible interrupt specified above. + * 1 - The PIRQ is not routed to the 8259. */
#define PIRQA 0x03 @@ -66,25 +68,24 @@ * Use 0x0ef8 for a bitmap to cover all these IRQ's. * Use the defined IRQ values above or set mainboard * specific IRQ values in your mainboards Config.lb. -*/ - + */ static void i82801ax_enable_apic(struct device *dev) { - uint32_t reg32; - volatile uint32_t *ioapic_index = (volatile uint32_t *)0xfec00000; - volatile uint32_t *ioapic_data = (volatile uint32_t *)0xfec00010; + u32 reg32; + volatile u32 *ioapic_index = (volatile u32 *)0xfec00000; + volatile u32 *ioapic_data = (volatile u32 *)0xfec00010;
/* Set ACPI base address (I/O space). */ pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
- /* Enable ACPI I/O and power management. */ - pci_write_config8(dev, ACPI_CNTL, 0x10); + /* Enable ACPI I/O range decode and ACPI power management. */ + pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
reg32 = pci_read_config32(dev, GEN_CNTL); - reg32 |= (3 << 7); /* Enable IOAPIC */ - reg32 |= (1 << 13); /* Coprocessor error enable */ - reg32 |= (1 << 1); /* Delayed transaction enable */ - reg32 |= (1 << 2); /* DMA collection buffer enable */ + reg32 |= (1 << 13); /* Coprocessor error enable (COPR_ERR_EN) */ + reg32 |= (3 << 7); /* IOAPIC enable (APIC_EN) */ + reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */ + reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */ pci_write_config32(dev, GEN_CNTL, reg32); printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
@@ -112,34 +113,22 @@ /* TODO: Explain/#define the real meaning of these magic numbers. */ }
-static void i82801ax_pirq_init(device_t dev, uint16_t ich_model) +static void i82801ax_pirq_init(device_t dev) { - /* Get the chip configuration */ + u8 reg8; config_t *config = dev->chip_info;
- if (config->pirqa_routing) { - pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); - } else { - pci_write_config8(dev, PIRQA_ROUT, PIRQA); - } + reg8 = (config->pirqa_routing) ? config->pirqa_routing : PIRQA; + pci_write_config8(dev, PIRQA_ROUT, reg8);
- if (config->pirqb_routing) { - pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing); - } else { - pci_write_config8(dev, PIRQB_ROUT, PIRQB); - } + reg8 = (config->pirqb_routing) ? config->pirqb_routing : PIRQB; + pci_write_config8(dev, PIRQB_ROUT, reg8);
- if (config->pirqc_routing) { - pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing); - } else { - pci_write_config8(dev, PIRQC_ROUT, PIRQC); - } + reg8 = (config->pirqc_routing) ? config->pirqc_routing : PIRQC; + pci_write_config8(dev, PIRQC_ROUT, reg8);
- if (config->pirqd_routing) { - pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing); - } else { - pci_write_config8(dev, PIRQD_ROUT, PIRQD); - } + reg8 = (config->pirqd_routing) ? config->pirqd_routing : PIRQD; + pci_write_config8(dev, PIRQD_ROUT, reg8); }
static void i82801ax_power_options(device_t dev) @@ -172,10 +161,10 @@ } }
-static void gpio_init(device_t dev, uint16_t ich_model) +static void gpio_init(device_t dev) { - pci_write_config32(dev, GPIO_BASE_ICH0_5, (GPIO_BASE_ADDR | 1)); - pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10); + pci_write_config32(dev, GPIO_BASE, (GPIO_BASE_ADDR | 1)); + pci_write_config8(dev, GPIO_CNTL, GPIO_EN); }
static void i82801ax_rtc_init(struct device *dev) @@ -190,7 +179,7 @@ reg8 &= ~(1 << 1); /* Preserve the power fail state. */ pci_write_config8(dev, GEN_PMCON_3, reg8); } - reg32 = pci_read_config32(dev, GEN_STS); + reg32 = pci_read_config32(dev, GEN_STA); rtc_failed |= reg32 & (1 << 2); rtc_init(rtc_failed);
@@ -213,7 +202,7 @@ pci_write_config16(dev, PCI_DMA_CFG, reg16); }
-static void i82801ax_lpc_decode_en(device_t dev, uint16_t ich_model) +static void i82801ax_lpc_decode_en(device_t dev) { /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB. * LPT decode defaults to 0x378-0x37F and 0x778-0x77F. @@ -221,13 +210,11 @@ * We also need to set the value for LPC I/F Enables Register. */ pci_write_config8(dev, COM_DEC, 0x10); - pci_write_config16(dev, LPC_EN_ICH0_5, 0x300F); + pci_write_config16(dev, LPC_EN, 0x300F); }
static void lpc_init(struct device *dev) { - uint16_t ich_model = pci_read_config16(dev, PCI_DEVICE_ID); - /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f);
@@ -237,13 +224,13 @@ i82801ax_enable_serial_irqs(dev);
/* Setup the PIRQ. */ - i82801ax_pirq_init(dev, ich_model); + i82801ax_pirq_init(dev);
/* Setup power options. */ i82801ax_power_options(dev);
/* Set the state of the GPIO lines. */ - gpio_init(dev, ich_model); + gpio_init(dev);
/* Initialize the real time clock. */ i82801ax_rtc_init(dev); @@ -255,7 +242,7 @@ isa_dma_init();
/* Setup decode ports and LPC I/F enables. */ - i82801ax_lpc_decode_en(dev, ich_model); + i82801ax_lpc_decode_en(dev); }
static void i82801ax_lpc_read_resources(device_t dev) @@ -293,15 +280,16 @@ .enable = i82801ax_enable, };
+/* 82801AA (ICH) */ static const struct pci_driver i82801aa_lpc __pci_driver = { .ops = &lpc_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = 0x2410, };
+/* 82801AB (ICH0) */ static const struct pci_driver i82801ab_lpc __pci_driver = { .ops = &lpc_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = 0x2420, }; -
Modified: trunk/src/southbridge/intel/i82801ax/i82801ax_pci.c ============================================================================== --- trunk/src/southbridge/intel/i82801ax/i82801ax_pci.c Fri Oct 8 18:40:23 2010 (r5924) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_pci.c Fri Oct 8 21:24:56 2010 (r5925) @@ -26,16 +26,12 @@
static void pci_init(struct device *dev) { - uint16_t reg16; + u16 reg16;
- /* Clear system errors */ - reg16 = pci_read_config16(dev, 0x06); - reg16 |= 0xf900; /* Clear possible errors */ - pci_write_config16(dev, 0x06, reg16); - - reg16 = pci_read_config16(dev, 0x1e); - reg16 |= 0xf800; /* Clear possible errors */ - pci_write_config16(dev, 0x1e, reg16); + /* Clear possible errors. */ + reg16 = pci_read_config16(dev, PCI_STATUS); + reg16 |= 0xf900; + pci_write_config16(dev, PCI_STATUS, reg16); }
static struct device_operations pci_ops = { @@ -46,15 +42,16 @@ .scan_bus = pci_scan_bridge, };
+/* 82801AA (ICH) */ static const struct pci_driver i82801aa_pci __pci_driver = { .ops = &pci_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = 0x2418, };
+/* 82801AB (ICH0) */ static const struct pci_driver i82801ab_pci __pci_driver = { .ops = &pci_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = 0x2428, }; -
Modified: trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.c Fri Oct 8 18:40:23 2010 (r5924) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.c Fri Oct 8 21:24:56 2010 (r5925) @@ -66,4 +66,3 @@ .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801AB_SMB, }; -
Modified: trunk/src/southbridge/intel/i82801ax/i82801ax_usb.c ============================================================================== --- trunk/src/southbridge/intel/i82801ax/i82801ax_usb.c Fri Oct 8 18:40:23 2010 (r5924) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_usb.c Fri Oct 8 21:24:56 2010 (r5925) @@ -18,8 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-/* This code should work for all ICH* southbridges with USB. */ - #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -53,4 +51,3 @@ .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801AB_USB, }; -