I checked out the coreboot code last time with debug traces that I have on my platform. In addition I read the atom e3800 family datasheet (from intel website).
I look at these files: https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/fsp_baytrai... https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/fsp_baytrai... https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/fsp_baytrai...
Where these defines are used : #define GPNCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPNCORE) #define IO_BASE_ADDRESS 0xfed0c000 #define IO_BASE_OFFSET_GPNCORE 0x1000
#define GPNCORE_COUNT 27
I saw in the intel atom datasheet the GPSCORE (from state S0) @0xfed0c000 and the GPSSUS (from state S5) @0xfed0e000. But I have never seen GPNCORE @0xfed0d000 (0xfed0c000 + 0x1000) in the Intel atom datasheet. Nevertheless these registers are initialized.
Can someone is aware about the GPIO GPNCORE registers on the atom E3800 family? Are they used on atom E3800 family ? If GPIOs GPNCORE are used where are they located ?
Thanks in advance for helping me Benoit