Zheng Bao (zheng.bao@amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1264
-gerrit
commit 6c9e7d7c6d8eb28b39c9bef1211031a88fd5773e Author: zbao fishbaozi@gmail.com Date: Mon Jul 23 19:49:40 2012 +0800
Limit the device field to 5 bits.
The field device in PCI_ADDRESS only takes 5 bits. So if the device number is more than 32, it will truncated to 5 bits. Before this patch, other pci devices will be incorrectly probed as processor node.
Change-Id: I64dcd4f4fda7b7080a9905dce580feb829584b94 Signed-off-by: Zheng Bao zheng.bao@amd.com Signed-off-by: zbao fishbaozi@gmail.com --- src/northbridge/amd/agesa/family15tn/northbridge.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index bc3877f..12aab33 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -120,8 +120,8 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
static device_t get_node_pci(u32 nodeid, u32 fn) { -#if MAX_NODE_NUMS == 64 - if (nodeid < 32) { +#if MAX_NODE_NUMS + CONFIG_CDB >= 32 + if ((CONFIG_CDB + nodeid) < 32) { return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); } else { return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn));