How about debuging/loading/using coreboot from a PCI device? Quote from Intel I/O Controller Hub 9 (ICH9) Family Datasheet:
CS—General Control and Status Register Offset Address: 3410–3413h Attribute: R/W, R/WLO Default Value: 00000yy0h (yy = xx0000x0b)Size: 32-bit
Boot BIOS Straps (BBS) — R/W. This field determines the destination of accesses to the BIOS memory range. The default values for these bits represent the strap values of GNT0# (bit 11) at the rising edge of PWROK and SPI_CS1#/GPIO58 (Desktop Only) /CLGPIO6 (Digital Office Only) (bit 10) at the rising edge of CLPWROK.
Bits 11:10 Description 0xb SPI 10b PCI 11b LPC When PCI is selected, the top 16MB of memory below 4GB (FF00_0000h to 11:10 FFFF_FFFFh) is accepted by the primary side of the PCI P2P bridge and forwarded to the PCI bus. This allows systems with corrupted or unprogrammed flash to boot from a PCI device. The PCI-to-PCI bridge Memory Space Enable bit does not need to be set (nor any other bits) in order for these cycles to go to PCI. Note that BIOS decode range bits and the other BIOS protection bits have no effect when PCI is selected. This functionality is intended for debug/testing only.
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