Rudolf Marek (r.marek@assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/359
-gerrit
commit a39f6bbf6b6994e7bb581bec75ca6f5514d780ee Author: Rudolf Marek r.marek@assembler.cz Date: Sun Oct 30 19:28:08 2011 +0100
Fix the build
Just fix the build and print error if buggy gppsb3 is encountered.
Change-Id: I8d5ef3777d8a7dfe311657707fbd9e7db81202dc Signed-off-by: Rudolf Marek r.marek@assembler.cz --- src/southbridge/amd/sr5650/pcie.c | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c index 37743ca..fbb2e31 100755 --- a/src/southbridge/amd/sr5650/pcie.c +++ b/src/southbridge/amd/sr5650/pcie.c @@ -224,7 +224,7 @@ static void switching_gpp3a_configurations(device_t nb_dev, device_t sb_dev) reg |= 0xFF0BAA0; break; default: /* shouldn't be here. */ - printk(BIOS_DEBUG, "Warning:gpp3a_configuration is not correct. Check you devicetree.cb\n"); + printk(BIOS_ERR, "Warning:gpp3a_configuration is not correct. Check you devicetree.cb\n"); break; } nbmisc_write_index(nb_dev, 0x26, reg); @@ -340,7 +340,7 @@ const u8 pGpp111111[] = {0x0E, 0x0E, 0x0E, 0x0E, 0, 0x0E, 0x0E}; static void gpp3a_cpl_buf_alloc(device_t nb_dev, device_t dev) { u8 dev_index; - u8 *slave_cpl; + u8 *slave_cpl = &pGpp111111; u8 value; struct southbridge_amd_sr5650_config *cfg = (struct southbridge_amd_sr5650_config *)nb_dev->chip_info; @@ -370,7 +370,7 @@ static void gpp3a_cpl_buf_alloc(device_t nb_dev, device_t dev) slave_cpl = (u8 *)&pGpp111111; break; default: /* shouldn't be here. */ - printk(BIOS_DEBUG, "buggy gpp3a_configuration\n"); + printk(BIOS_ERR, "buggy gpp3a_configuration\n"); break; }
@@ -411,7 +411,7 @@ static void gpp12_cpl_buf_alloc(device_t nb_dev, device_t dev) set_pcie_enable_bits(dev, 0x10, 0x3f << 8, value << 8); set_pcie_enable_bits(dev, 0x20, 1 << 11, 1 << 11); } else { - printk(BIOS_DEBUG, "buggy gpp configuration\n"); + printk(BIOS_ERR, "buggy gpp configuration\n"); } }