Really nice (and CLEAN...) patch :)
i do have two questions -
1. in sdram_set_spd_registers(), what is the correct order of the 3 following commands:
spd_set_dram_size(); set_dram_buffer_strength(); set_dram_timing();
since ive noticed its not the same as in other related intel northbridges (not that it counts for something...). i would assume timing & strength should be called before setting the size. no?
2. also, in do_ram_command(), i have no idea how you got those addr_offset from... can you please elaborate or link me to the proper page on the datasheet (or similar)?
On Fri, Nov 21, 2008 at 7:15 PM, Uwe Hermann firstname.lastname@example.org wrote:
On Fri, Nov 21, 2008 at 05:04:26PM +0100, Peter Stuge wrote:
Uwe Hermann wrote:
i810: Add support for multiple DIMMs, both single-sided and
as well as most (all?) combinations thereof.
Drop some unused code, the unused row_offset variable, and obsolete
Also, fix a typo (thanks to Stefan Reinauer for noticing).
This is tested on the MSI MS-6178 with a number of different DIMM combinations and so far all of them worked fine.
Acked-by: Peter Stuge email@example.com
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