the following patch was just integrated into master: commit 364609066b3ad1be8c5827405d6d3813c72a65a6 Author: Sebastian Andrzej Siewior bigeasy@linutronix.de Date: Fri Oct 26 19:01:45 2012 +0200
northbridge/sch: read the size of main memory from the proper register
I don't know if the size main memory supposed to be in PCI(0,0) reg 0x9c but it is not written there. The size of memory is written in src/northbridge/intel/sch/raminit.c to SCH port(2, 8, 4) (look for "Setting up TOM").
Change-Id: Iea04a5185bda56f61d1c382533d5a0dac429ebbd Signed-off-by: Sebastian Andrzej Siewior bigeasy@linutronix.de
Reviewed-By: Patrick Georgi patrick@georgi-clan.de at Fri Oct 26 19:26:25 2012, giving +2 Build-Tested: build bot (Jenkins) at Fri Oct 26 20:08:16 2012, giving +1 Reviewed-By: Stefan Reinauer stefan.reinauer@coreboot.org at Fri Oct 26 19:28:13 2012, giving +2 See http://review.coreboot.org/1629 for details.
-gerrit