Carl-Daniel Hailfinger wrote:
suggest a setting which makes flashrom skip all parallel flash
chips, to remove any need for calibration.
That would break some Winbond LPC flash chips which require a few
milliseconds of delay between JEDEC toggle reads on erase.
And we also noticed that some SPI chips will react badly (corruption)
to a too tight RDSR instruction schedule.
Yay. I guess they would be disabled too, unless calibration has run.
Given that LPC/FWH/SPI flash chips usually tolerate
expected delays without problem, you could hook up programmer_delay
to udelay and save a second or so for calibration if you don't need
That sounds good!
(To be more
precise, the deciding factor is whether the chip is on
the local bus, or if there are some bus master(s) in between, but
that's generally equivalent to parallel vs. all others.)
Network cards with parallel flash would be classified as "local bus"?
I believe bridges can make things more complicated. The assumption is
that any bus master will always ensure correct timing for the bus
where the chip is connected. You mentioned that there are exceptions,
to that, but I think it'll hold in general. A bridge in a PCI chip
that decodes into ROM may or may not ensure correct timing. I think
it would have to be set on a per-chip basis.