Dear coreboot folks,
Am 29.12.22 um 14:05 schrieb Paul Menzel:
A colleague made me aware of the presentation *The OSF on Supermicro's platform* [1] by the Supermicro employees Hancock Chang and Simon Chou¹ at the OCP Global Summit 2022 this October. This is great news. I would have loved to also read about this on the coreboot mailing list.
In the talk, the board Supermicro X12SPW is mentioned, and that it’s planned for the X13 series. One of our suppliers responded though, that systems with coreboot are currently not generally available, but it’s something Supermicro offers to ODMs or for projects with large volumes.
The slide *Call to Action* contains:
Come and collaborate with Supermicro
Collaboration would be great. A first step would be, if Supermicro (engineers) would get in touch with the coreboot project/community on the mailing list, and also upstreamed their work and contributed their improvements. Judging from the presented times, there is still a lot of potential to unlocked, and where the coreboot community already has a lot of experience in to share to make sure, the Supermicro boards work even better.
As a follow-up, Simon pushed change-sets enabling 4th Gen Intel Xeon Scalable processors (formerly codenamed Sapphire Rapids) for review [3]. The added customer reference board (CRB) is named Archer City [4].
Kind regards,
Paul
PS: OpenBMC patches are already being sent upstream [2].
¹ Hopefully correct addresses in Cc. At least my test message did not bounce.
[2]: https://lore.kernel.org/openbmc/20221229100155.2954455-1-ryans@supermicro.co...]: https://review.coreboot.org/q/topic:spr-enable