[coreboot] Re: Apollo Lake cannot load coreboot

[Anatolii Vorobev]

Hi Wolfgang,
We have TI650944 PMIC and LPDDR4 memory down configuration. SPI flash chip JDEC ID do present in IFD VSCC table. SPI boot strap is selected, TXE ROM Bypass is disabled.
I program flash device with Dediprog programmer.
Yes, I can see __FMAP__ signature in the dumped binary at 0x300000 offset.

I have a question. Is it TXE that copies bootblock and romstage into RAM(cache)?

I also wonder what differences can be between UP2 and my board? May be I should preprogram something into FPF (signing keys maybe) before loading coreboot? Can it be related to Boot Guard?

Best Regards,
Anatolii Vorobev
Lead Developer, Firmware | WayRay
[e-mail] | http://wayray.com
[phone] (RU)

From: Wolfgang Kamp - datakamp 
Sent: Thursday, December 3, 2020 11:40 AM
To: Anatolii Vorobev 
Cc: [e-mail]
Subject: AW: [coreboot] Re: Apollo Lake cannot load coreboot

Hi Anatolii,

If you search the web for “apollolake implementation – coreboot”, you will find interesting information about the Apollo Lake boot process. The IFD will be processed from the internal microcontroller which looks for the correct Flash device and the PMIC. The PMIC must be the TI chip TPS65094x in the case of using the UP Squared board BIOS components. To boot from SPI the SOC_COM1_TXD (eMMC boot) signal must be pulled low and the SOC_COM1_RTS_N (SPI boot) signal must be pulled high.
How do you program the on board FLASH device?
If you dump the binary contents you can see –FMAP-- signature at 0x300000?

Kind regards,
Wolfgang

Von: Anatolii Vorobev [mailto:[e-mail]]
Gesendet: Mittwoch, 2. Dezember 2020 13:44
An: Wolfgang Kamp - datakamp <[e-mail]>
Cc: [e-mail]
Betreff: RE: [coreboot] Re: Apollo Lake cannot load coreboot

Hi Wolfgang,
If I read memory at address 0xFF00 0000-0xFFFE 0000 after SPI is initialized by bootblock_soc_early_init() then I will get only 0xFF bytes. So there is no mapped SPI image there – it is empty. But I should see at least IFD at 0xFF00 0000-0xFF00 1000, am I right?

The mainboard I’m debugging is not UP Squared, the schematics are just a bit resembling (as far as I see, because UP2 design files are disclosed). That’s why there are some hardware differences that lead to problems above. Is it GPIO settings or bootstraps? What would you suggest me to check first?

Best Regards,
Anatolii Vorobev

From: Wolfgang Kamp - datakamp <[e-mail]>
Sent: Tuesday, December 1, 2020 5:33 PM
To: Anatolii Vorobev <[e-mail]>
Cc: [e-mail]
Subject: AW: [coreboot] Re: Apollo Lake cannot load coreboot

Hi Anatolii,

In this early stage there is no RAM initialized. The SPI Flash is memory mapped starting at 0xFF00 0000 if the FLASH size is 16M, which is on UP Squared default.  On address 0xFF30 0000 (0x300000 relative to FLASH start address) starts FMAP. You will find the header –FMAP—on this position. With an in circuit programmer like DEDIPROG 100 you can check this on UP Squared board.

Kind regards,
Wolfgan

Von: Anatolii Vorobev [mailto:[e-mail]]
Gesendet: Dienstag, 1. Dezember 2020 12:44
An: Maxim Polyakov <[e-mail]>
Cc: [e-mail]
Betreff: [coreboot] Re: Apollo Lake cannot load coreboot

Hi, Maxim. Sure, I’ve attached .config file.
Here is cbfstool output:

./build/cbfstool build/coreboot.rom print
FMAP REGION: COREBOOT
Name                           Offset     Type           Size   Comp
cbfs master header             0x0        cbfs header        32 none
fallback/romstage              0x80       stage           48164 none
cpu_microcode_blob.bin         0xbd00     microcode       48128 none
fallback/ramstage              0x17980    stage          106068 none
vgaroms/seavgabios.bin         0x31840    raw             28160 none
config                         0x386c0    raw               283 none
revision                       0x38840    raw               681 none
fallback/dsdt.aml              0x38b40    raw              6338 none
fspm.bin                       0x3a480    fsp            364544 none
vbt.bin                        0x934c0    raw              1299 LZMA (6154 decompressed)
payload_revision               0x93a40    raw               235 none
(empty)                        0x93b80    null             1048 none
fsps.bin                       0x93fc0    fsp            176128 none
fallback/postcar               0xbf000    stage           22064 none
fallback/payload               0xc4680    simple elf      69275 none
payload_config                 0xd5580    raw              1760 none
(empty)                        0xd5cc0    null         11137752 none
bootblock                      0xb74fc0   bootblock       32768 none

Best Regards,
Anatolii Vorobev

From: Maxim Polyakov <[e-mail]>
Sent: Tuesday, December 1, 2020 2:05 PM
To: Anatolii Vorobev <[e-mail]>
Cc: [e-mail]
Subject: Re: [coreboot] Apollo Lake cannot load coreboot

Hi!

Could you please send your .config ?

The following command will help you find out which sections have been added to the image:

(coreboot dir)$ ./build/cbfstool build/coreboot.rom print

Please send the output
// Regards,
// Max

вт, 1 дек. 2020 г. в 13:13, Anatolii Vorobev <[e-mail]>:
Dear community,
I’m trying to bring up custom motherboard with Apollo Lake e3950 SoC. The first thing I’ve tried is flashed UP Squared-based BIOS compiled using this instructions: https://doc.coreboot.org/mainboard/up/squared/index.html
After I run the motherboard it showed this uart0 output:

coreboot-4.12-4087-g6aaf7db719-dirty Tue Nov 17 09:50:24 UTC 2020 bootblock starting (log level: 7)...
No FMAP found at 300000 offset.
No FMAP found at 300000 offset.
POST: 0xe0
Couldn't load romstage.

After some time spent trying to figure out the reason of such problem I found out that bootblock cannot load FMAP into RAM. I printed out some parts of ram where romstage and FMAP should be and there where only 0xff values. Looks like bootblock can’t map SPI flash data to RAM although flash image has romstage and FMAP regions. The strange thing is that bootblock is loaded ok but any further load (FMAP) fails. Any ideas what can be the cause of this and how can I debug this thing?

PS I tried  flashing another BIOS (from AMI) and it passes CAR stage, FSP stage, it even successfully initializes/trains DDR and so on. But coreboot BIOS somehow fails on the very early stages.

Best Regards,
Anatolii Vorobev
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