Stefan Reinauer wrote:
Are you configuring your Super IO correctly? Did you call your Super IO init function in auto.c? Compare your settings with the output of superiotool -d
Ok, progress report time. After careful analysis I figured out nothing in the auto.c was actually getting compiled into the resulting rom binary, hence I wasn't seeing the port accesses I expected on the LPC bus. Some of the subroutines got compiled in anyway, so it looked like it was doing something sensible... It took a while to figure out that the build-system had been replaced, but the old romcc builds have not been updated to the new system, causing the auto.c to get compiled with distribution gcc, resulting in a successful build but completely broken binary.
After upgrading the target to use the new romcc makefile, the vt8237r ddr init wouldn't compile, taking a few minutes before dumping several pages worth of debug and stating there weren't enough registers. Oddly enough, after adjusting the super-io initialization, the ddr init started suddenly compiling, but at linking phase I get complaints about .text overlapping .id and the end of the rom by about few kilobytes. The BIOS_IMAGE_SIZE fix suggested on the Wiki had no effect on build. Unable to find anything else to cut, after verifying the memories read as CAS 2.5, I commented out support for other CAS (This isn't really acceptable on the long run, because I know the boards have been made with memories having different CAS latency).
Now, though, the DDR initialization routine is giving out the following results, repeatedly. I haven't yet delved deeply into the datasheets, but it seems to me like there's something wrong with most of the parameters, especially since this board has 256MiB of memory on four 512Mbit DDR333 (2.5-3-3) chips with 8M x 16 x 4banks on each. Is it likely I need to port smbus_fixup for this to work? The north & southbridge initializations are otherwise unmodified as of yet. Also, are there any suggestions to solve the overlapping segments issue without disabling essential functionality, or any luck getting CAR to work on Eden ESP/C3?
vt8623 init starting Detecting Memory Number of Banks 1b Number of Rows 0c No Columns 45 MA type 00 Bank 0 (*16 Mb) 01 No Physical Banks 00 Total Memory (*16 Mb) 01 CAS Supported Cycle time at CL X (nS)80 Cycle time at CL X-0.5 (nS)01 Cycle time at CL X-1 (nS)f1 Starting at CAS 2.5 tRP 00 tRCD 40 tRAS 00FS 0x00
Low Bond 00 High Bondaf Setting DQS delay74vt8623 done 00:06 11 23 31 06 00 30 22 00 00 00 06 00 00 00 00 10:08 00 00 d0 00 00 00 00 00 00 00 00 00 00 00 00 20:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30:00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 40:00 18 88 80 82 44 00 0FS 0x00 0 1a b9 88 80 82 44 00 00 50:c8 de cf 88 e0 07 00 00 00 00 01 01 01 01 00 00 60:02 ff 00 30 24 32 01 2a 42 2d 86 58 00 44 00 00 70:82 c8 00 01 01 08 50 00 01 00 00 00 00 00 00 10 80:0f c0 00 00 80 00 00 00 02 00 00 00 00 00 00 00 90:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0:02 c0 20 00 07 02 00 1f 04 00 00 00 2f 02 04 00 b0:00 00 00 00 80 00 00 00 88 00 00 04 00 00 00 00 c0:01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0:00 00 00 00 00 00 01 00 40 00 00 00 00 00 00 00 f0:00 00 00 00 00 00 11 13 00 00 00 00 00 00 00 00 AGP doing early_mtrr Copying coreboot to RAM.