Re: [coreboot] [patch] add MSI MS-7135 support, try two

[Carl-Daniel Hailfinger]

On 02.02.2008 05:21, [e-mail] wrote:
> Initial support for MSI MS-7135 (K8N Neo3) mainboard.
>
> Signed-off-by: Jonathan A. Kollasch
>
> --- src/mainboard/msi/ms7135/mptable.c	(revision 0)
> +++ src/mainboard/msi/ms7135/mptable.c	(revision 0)
> [...]
>
> +/*I/O Ints:		Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN# */
> smp_write_intsrc(mc, mp_ExtINT,
> 	 MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
> 	 bus_isa, 0x0, apicid_ck804, 0x0);
> smp_write_intsrc(mc, mp_INT,
> 	 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
> 	 bus_isa, 0x1, apicid_ck804, 0x1);
> smp_write_intsrc(mc, mp_INT,
> 	 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
> 	 bus_isa, 0x0, apicid_ck804, 0x2);
> smp_write_intsrc(mc, mp_INT,
> 	 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
> 	 bus_isa, 0x3, apicid_ck804, 0x3);
> smp_write_intsrc(mc, mp_INT,
> 	 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
> 	 bus_isa, 0x4, apicid_ck804, 0x4);
> smp_write_intsrc(mc, mp_INT,
> 	 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
> 	 bus_isa, 0x6, apicid_ck804, 0x6);
> smp_write_intsrc(mc, mp_INT,
> 	 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
> 	 bus_isa, 0x7, apicid_ck804, 0x7);
> smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
> 	 bus_isa, 0x8, apicid_ck804, 0x8);
> smp_write_intsrc(mc, mp_INT,
> 	 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
> 	 bus_isa, 0x9, apicid_ck804, 0x9);
> smp_write_intsrc(mc, mp_INT,
> 	 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
> 	 bus_isa, 0xc, apicid_ck804, 0xc);
> smp_write_intsrc(mc, mp_INT,
> 	 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
> 	 bus_isa, 0xd, apicid_ck804, 0xd);
> smp_write_intsrc(mc, mp_INT,
> 	 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
> 	 bus_isa, 0xe, apicid_ck804, 0xe);
> smp_write_intsrc(mc, mp_INT,
> 	 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
> 	 bus_isa, 0xf, apicid_ck804, 0xf);
> // Onboard ck804 smbus
> smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[0], ((sbdn + 1) << 2) | 1, apicid_ck804, 10); /* (this seems odd) */
> // Onboard ck804 USB 1.1
> smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[0], ((sbdn + 2) << 2) | 0, apicid_ck804, 23);
> // Onboard ck804 USB 2.0
> smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[0], ((sbdn + 2) << 2) | 1, apicid_ck804, 23);
> // Onboard ck804 AC-97
> smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[0], ((sbdn + 4) << 2) | 0, apicid_ck804, 23);
> // Onboard ck804 SATA 0
> smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[0], ((sbdn + 7) << 2) | 0, apicid_ck804, 20);
> // Onboard ck804 SATA 1
> smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[0], ((sbdn + 8) << 2) | 0, apicid_ck804, 21);
> // Onboard ck804 NIC
> smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[0], ((sbdn + 10) << 2) | 0, apicid_ck804, 22); // should be 21
> /* legacy PCI */
> smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[1], (7 << 2) | 0, apicid_ck804, 17);
> smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[1], (7 << 2) | 1, apicid_ck804, 18);
> smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[1], (7 << 2) | 2, apicid_ck804, 19);
> smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[1], (7 << 2) | 3, apicid_ck804, 16);
> /* --- */
> smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[1], (8 << 2) | 0, apicid_ck804, 18);
> smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[1], (8 << 2) | 1, apicid_ck804, 19);
> smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[1], (8 << 2) | 2, apicid_ck804, 16);
> smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[1], (8 << 2) | 3, apicid_ck804, 17);
> /* --- */
> smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[1], (9 << 2) | 0, apicid_ck804, 19);
> smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[1], (9 << 2) | 1, apicid_ck804, 16);
> smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[1], (9 << 2) | 2, apicid_ck804, 17);
> smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[1], (9 << 2) | 3, apicid_ck804, 18);
> /* PCI-E x1 port */
> smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[2], (0 << 2) | 0, apicid_ck804, 19);
> /* XXX fill in f1-3 */
> /* PCI-E x16 port */  /* XXX fix me */
> smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[3], (0 << 2) | 0, apicid_ck804, 18);
> /* XXX fill in f1-3 */
>
> +/*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
> smp_write_lintsrc(mc, mp_ExtINT,
> 	 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
> 	 bus_ck804[0], 0x0, MP_APIC_ALL, 0x0);
> smp_write_lintsrc(mc, mp_NMI,
> 	 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
> 	 bus_ck804[0], 0x0, MP_APIC_ALL, 0x1);

Could you simplify the code above with macros like in r3035 and r3041? That would make the code easier to review and maintain.

Regards,
Carl-Daniel