[LinuxBIOS] compiler error isolated

[Doug Bell]

The attached revised spd.c compiles as is. When you
have :

subtotal=dev+0;  // it works 
subtotal=dev;    // it fails ( internal compiler error
- rhs not used )

Amazing but true. What's going on here?

--- Doug Bell  wrote:
> The attached spd.c contains functions called from my
> raminit.c's sdram_set_spd_registers(). Raminit.c is
> #included into auto.c. I've tried various
> workarounds
> including putting all the code in spd.c under one
> function, getting rid of the device_t ctl, etc. but
> compilation doesn't yet work. Ideas appreciated.
>
> Thanks, dB
>
> --- Doug Bell  wrote:
> > Beyond that, there was one version in which I
>
> simply
> > switched the order of declaration of variables to
> > make
> > it compile:
> >
> > // unsigned char row,col; // broken
> > unsigned char col,row; // works
> >
> > In another test run........
> > //if ( total < c) total+=div; // failed
> >
> > if ( total < c) subtotal+=div; // was ok
> > total=subtotal;
> >
> > Ron / Eric  - What is the best way to proceed on
> > this?
> > What info would you want? I don't think I'm doing
> > anything bizarre, maybe 4 chars declared, no deep
> > levels of functions.
> >
> > --- Doug Bell  wrote:
> > > I had one version of code where it failed on a
> >
> > line
> > > like:
> > > if (speed==100) speed=0;
> > >
> > > but problem disappeared if I did :
> > > if (speed==100) speed2=0;
> > >
> > > This may have been a factor in the first
>
> reporting
> > > of
> > > the problem as well.
> > >
> > > -dB
> > >
> > > --- Doug Bell  wrote:
> > > > It seems to not be related to register
> >
> > allocation,
> > > > how
> > > > many layers of functions,  or code size, but
>
> to
> > > > nested
> > > > if statements or variations thereof, e.g. if (
> > > > (condition a) && ( condition b) ) ....
> > > >
> > > > /home/dbell # uname -a
> > > > Linux Doug 2.6.9 #1 Tue Jan 11 17:26:41 UTC
>
> 2005
> > > > i686
> > > > Intel(R) Pentium(R) 4 CPU 1500MHz GenuineIntel
> > > > GNU/Linux
> > > >
> > > > Target is via epia-sp, under development but
> >
> > close
> > > > to
> > > > an alpha release with some open items.
> > > >
> > > > BTW, is there any documentation regarding what
> > > > limitations romcc has (e.g. multidimensional
> > >
> > > arrays
> > > > not allowed, etc )?
> > > >
> > > > Thanks, Doug
> > > >
> > > > --- ron minnich  wrote:
> > > > > On 9/26/05, Doug Bell
>
> wrote:
> > > > > > 0x8360d58 phi Internal compiler error:
> >
> > Cannot
> > > > > > find block dominated by 0x82ba9a8
> > > > > >
> > > > > > Any ideas on workarounds / fixes here? Is
>
> am
> > I
> > > > > running
> > > > > > out of registers or some other problem?
> > > > >
> > > > > can you tell us more about the environment,
> > > > > uname -a
> > > > > distro, and linuxbios target?
> > > > >
> > > > > ron
> > > > > >
> > > > >
> > > > > LinuxBIOS mailing list
> > > > > [e-mail]
>
> http://www.openbios.org/mailman/listinfo/linuxbios
> > > > __________________________________ 
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> >
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> > > >
> > >
> > > __________________________________ 
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>
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> > >
> >
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>
> //ALL SPD STUFF IS IN PROGRESS
>
> #include <device/pci_ids.h>
>
> void spd_dram_presence( void ){}
> void spd_dram_size( void ) {}
> void spd_dram_other( void ) {}
> //unsigned char spd_trp( void ) { 
> //	return 0;
> //}
>
> unsigned char spd_dram_timings( void ) { 	// set
> dram bus speed based off CPU's FSB and SPD byte 9
>
> print_info("sdram_spd_dram_timings..........\r\n");
>
> device_t ctl = (device_t) 0;
>    unsigned char c;
>    unsigned char col,row; 
>    unsigned char freq;
>    unsigned char reg;
>    unsigned char i;
>
> // find CPU controlller - the CN400 device 0
> function 3 so use virtual device function 2
>    pci_write_config8(0,0x4f,1); // but first allow it
> to be seen using multiple function enable
>
> ctl = pci_locate_device(
>    	PCI_ID(
> PCI_VENDOR_ID_VIA,PCI_DEVICE_ID_VIA_CN400_2 ),
>    	0 );
>    c=pci_read_config8(ctl,0x54);
>
> print_debug_hex8(c);
>    print_debug(" is CPU FSB\r\n");
>
> unsigned char fsb;
>    fsb =  c >> 5;
>
> print_debug_hex8(fsb);
>    print_debug(" = fsb \r\n");
>
> c=smbus_read_byte(SMBUS_MEM_DEVICE_START, 9); //
> one DIMM
>    print_debug_hex8(c);
>    print_debug(" returned as spd data for register
> 9\r\n");
>
> // decide supported dram speed per PG
>    unsigned char speed;
>    if ( c <= 0x50 ) {
>    	speed = 200;
>    }
>    else if ( c <= 0x60 ) {
>    	speed = 166;
>    }
>    else if ( c <= 0x75 ) {
>    	speed = 133;
>    }
>    else {
>    	speed = 100;
>    }
>    print_debug_hex8(speed);
>    print_debug(" = speed\r\n");
>
> //revisit
>    static const unsigned char timing[5][5] = {
> 	//dram	100	133	166	200	266
>
> 		{ 0xff,	1,	5,	9,	0xff},   	// row 0 cpu=100
> 		{ 0xff,	0,	1,	5,	0xff}, 	// row 1 cpu=133
> 		{ 0xff,	2,	0,	1,	0xff}, 	// row 2 cpu=166
> 		{ 0xff,	6,	2,	0,	0xff},	// row 3 cpu=200
> 		{ 0xff,	0x0a,	6,	2,	0xff}, 	// row 4 cpu=266
>
> 				}; // on datasheet there seems to be two
>
> values for cpu=266 dram=133
>    // also see p. 30 of PG, looks like 0x0a is right
>    // note no 100 or 266 dram speeds
>
> // important - revise fsb and speed for correct
> indexing into table
>    if ( fsb == 0 ) 	row=0;  // 100 
>    else if ( fsb == 1 ) 	row=1;  // 133
>    else if ( fsb == 3 ) 	row=2;  // 166 note value 
>    else if ( fsb == 2 ) 	row=3;  // 200 note value 
>    else if ( fsb == 4 ) 	row=4;  // 266
>    else {
>    	print_debug(" bad fsb setting\r\n");
>    	return -1;
>    }
>    if ( speed == 100 ) 		col=0;  // 100 
>    else if ( speed == 133 ) 	col=1;  // 133
>    else if ( speed == 166 ) 	col=2;  // 166
>    else if ( speed == 200 ) 	col=3;  // 200
>    else if ( speed == 266 ) 	col=4;  // 266
>    else {
>    	print_debug(" bad speed setting\r\n");
>    	return -2;
>    }
>
> freq=timing[row][col];
>    print_debug_hex8(freq);  // row / col
>    print_debug("  = timing table value \r\n");
>
> if ( freq==0xff ) {
>    	print_debug(" bad timing value\r\n");
>    	return -3;
>    }
>
> ctl = pci_locate_device(
>    	PCI_ID(
> PCI_VENDOR_ID_VIA,PCI_DEVICE_ID_VIA_CN400_3 ),
>    	0 );
>    c=pci_read_config8(ctl,0x68); 
>    print_debug_hex8(c);
>    print_debug(" = r68\r\n");
>    c &=0xf0;
>    c|=freq;
>    pci_write_config8(ctl,0x68,c); 
>    print_debug_hex8(c);
>    print_debug(" = r68 written \r\n");
>
> /***************** BANK INTERLEAVE ***************/
>
> c=smbus_read_byte(SMBUS_MEM_DEVICE_START, 17); 
>    if ( ! (c==2 || c==4 ) ) {
>    	print_info("unexpected reg 17 value\r\n");
>    	return -4;
>    }
>    	
>    reg=pci_read_config8(ctl,0x69);
>    reg &=0x3f;
>    reg |= (c<<6);
>    pci_write_config8(ctl,0x69,reg);
>    print_debug_hex8(reg);
>    print_debug(" = r69 written \r\n");

/*********************************************************/
> print_info("sdram_set_spd_registers done\r\n");
>    return 0;
> }
>
> unsigned char spd_trp( void ) {
>
> // GRAB A BOGUS NON-CONST VALUE FOR COMPILATION TEST
> ONLY!!!
>    unsigned char
> speed=smbus_read_byte(SMBUS_MEM_DEVICE_START, 9);
>
> print_info("spd_trp.........\r\n");
>
> device_t ctl = (device_t) 0;
>
> unsigned char div=0;
>    unsigned char i;
>    unsigned char total,subtotal;
>    unsigned char c;
>
> // find CPU controlller - the CN400 device 0
> function 3 so use virtual device function 2
>    pci_write_config8(0,0x4f,1); // but first allow it
> to be seen using multiple function enable
>
> ctl = pci_locate_device(
>    	PCI_ID(
> PCI_VENDOR_ID_VIA,PCI_DEVICE_ID_VIA_CN400_3 ),
>    	0 );
>
> /*************** tRP
> **********************************/
>
> if ( speed == 100 ) 		div=0x28;  // divisor
>    else if ( speed == 133 ) 	div=0x1e;  
>    else if ( speed == 166 ) 	div=0x18;  
>    else if ( speed == 200 ) 	div=0x14;  
>    else {
>
> //		print_debug(" bad tRP speed setting\r\n");
>    	return -5;
>    }

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